This paper presents Disydent, a framework dedicated to system-on-a-chip (SoC) platform-based design for shared memory multiple instructions multiple data (MIMD) architectures. We define a platform-based design problem as a triplet (system, application, constraints) where the system is both an operating system (OS) and a hardware (HW) template that can be enhanced with dedicated coprocessors. Our contributions are: 1) the definition of a complete flow for platform-based design, from application to integration including all necessary intermediate steps and 2) a set of tightly bound operational tools to implement the flow. Disydent is based on four tools. The distributed process network (DPN) is a C library for describing Kahn process network (KPN)-based applications. The asynchronous serial interface mode register 0 (ASIM0) is a multiprocessor target platform running a microkernel. This platform can be enhanced with coprocessors generated by the user-guided high-level synthesis (UGH) tool. Cycle accurate system simulator (CASS) is a high-performance cycle-accurate simulator. The main steps of the design flow are KPN modeling, functional validation, design space exploration, high-level synthesis, and temporal validation. The design flow starts by modeling the application as a KPN. This initial description is done in C using the DPN library. The functional validation is performed by running the initial description directly on the host. Without modifying the initial description, the user can simulate a HW/software (SW) partitioning by indicating the number of processors and the processes that are to be migrated to HW. This simulation is done at the cycle-accurate level for the whole system, except for the migrated processes for which the user must provide estimated time models. The description of the processes that are selected for HW implementation must be translated into a subset of C and then synthesized. This new description is still compatible with the DPN library, so it can be used for functional validation. The temporal validation is done at the cycle-accurate level using the initial description for the SW processes and cycle-accurate models automatically generated from the C subset description for the HW processes. Disydent's strength relies on its formal KPN model that ensures a behavior that is independent of the overall system scheduling, its fast cycle-accurate validation that is several orders of magnitude faster than classical event-driven simulators, and its single description of a process that is used as input of DPN, CASS, and UGH.

A quantitative method for designing application specific integrated (sub)systems is presented. The method uses a general-purpose silicon assembler-ALMA (Approche d'un Langage de Micro-Architecture). We illustrate this approach by the example of a dictionary machine that consists of n processing elements working in parallel. An analysis of the effect of several generic parameters on the performance and the size of the silicon parts exemplifies the quantitative approach to cost/performance tradeoffs that is offered by ALMA.>

ALMA presents itself like a shell over a CAD framework. It mainly aims at portable description (independent on CAD framework); rapid system modelling (using a powerful temporal and functional simulator), and quick realization (using a sequential language manipulating hardware resources like registers, ALUs). The ALMA strongest point is its practical side. It offers entry points within the system at two different levels. The first level gives the possibility to install new resources in the input language. Except on installation phases for these new resources, this level is a portable entry. The second level is to directly bring into the simulator manually designed blocks by describing their models. Such a feature is of course not portable. Finally, ALMA relations to CAD frameworks look a little bit like Unix relations to computers. ALMA is a general purpose kernel, but this kernel is open, and the user can focus itself onto a specific application domain.>