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Anvesh Komuravelli

dblp:10/6764 · DBLP profile ↗
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14ranked-venue papers
10as first author
0since 2021 · last 2016
0000-0002-0927-2075ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Theory of computation · 8 · 7 first-authorSoftware engineering, systems software and programming languages · 5 · 4 first-authorSystems, architecture and hardware · 3 · 1 first-authorSecurity and privacy · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
4 papers
Automated reasoning and model checking · 87% Logic in computer science · 13%
Software engineering, system software, and programming languages
3 papers
Program verification · 68% Programming languages and type systems · 32%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Automated reasoning and model checking › model checking
software model checking
0.422014
SMT-Based Model Checking for Recursive Programs · CAV 2014
Automatic Abstraction in SMT-Based Unbounded Software Model Checking · CAV 2013
Program verification › model checking
software model checking
0.212015
The SeaHorn Verification Framework · CAV (1) 2015
Programming languages and type systems › control structures › recursion
recursive programs
0.212014
SMT-Based Model Checking for Recursive Programs · CAV 2014
Program verification
recursive program verification
0.212014
SMT-Based Model Checking for Recursive Programs · CAV 2014
Automated reasoning and model checking › model checking › symbolic model checking
SMT-based model checking
0.212014
SMT-Based Model Checking for Recursive Programs · CAV 2014
Automated reasoning and model checking
abstraction refinement
0.112012
Assume-Guarantee Abstraction Refinement for Probabilistic Systems · CAV 2012
Automated reasoning and model checking › compositional verification
assume-guarantee reasoning
0.112012
Assume-Guarantee Abstraction Refinement for Probabilistic Systems · CAV 2012
Automated reasoning and model checking › model checking
probabilistic model checking
0.112012
Assume-Guarantee Abstraction Refinement for Probabilistic Systems · CAV 2012

Methods — techniques the papers use, named apart from their topics

SMT solving · 0.7state-space partitioning · 0.1probabilistic model checking · 0.1assume-guarantee reasoning · 0.1
YearPublicationVenuePosition
2016 SMT-based model checking for recursive programs
Anvesh Komuravelli, Arie Gurfinkel, Sagar Chaki
Formal Methods Syst. Des.1
2015 The SeaHorn Verification Framework
Arie Gurfinkel, Temesghen Kahsai, Anvesh Komuravelli, Jorge A. Navas
CAV (1)3
2015 Compositional Verification of Procedural Programs using Horn Clauses over Integers and Arrays
abstract
We present a compositional SMT-based algorithm for safety of procedural C programs that takes the heap into consideration as well. Existing SMT-based approaches are either largely restricted to handling linear arithmetic operations and properties, or are non-compositional. We use Constrained Horn Clauses (CHCs) to represent the verification conditions where the memory operations are modeled using the extensional theory of arrays (ARR). First, we describe an exponential time quantifier elimination (QE) algorithm for ARR which can introduce new quantifiers of the index and value sorts. Second, we adapt the QE algorithm to efficiently obtain under-approximations using models, resulting in a polynomial time Model Based Projection (MBP) algorithm. Third, we integrate the MBP algorithm into the framework of compositional reasoning of procedural programs using may and must summaries recently proposed by us. Our solutions to the CHCs are currently restricted to quantifierfree formulas. Finally, we describe our practical experience over SV-COMP'15 benchmarks using an implementation in the tool SPACER.
Anvesh Komuravelli, Nikolaj S. Bjørner, Arie Gurfinkel, Kenneth L. McMillan
FMCAD1
2014 SMT-Based Model Checking for Recursive Programs
Anvesh Komuravelli, Arie Gurfinkel, Sagar Chaki
CAV1
2013 Automatic Abstraction in SMT-Based Unbounded Software Model Checking
Anvesh Komuravelli, Arie Gurfinkel, Sagar Chaki, Edmund M. Clarke
CAV1
2012 Assume-Guarantee Abstraction Refinement for Probabilistic Systems
Anvesh Komuravelli, Corina Pasareanu, Edmund M. Clarke
CAV1
2012 Learning Probabilistic Systems from Tree Samples
abstract
We consider the problem of learning a non-deterministic probabilistic system consistent with a given finite set of positive and negative tree samples. Consistency is defined with respect to strong simulation conformance. We propose learning algorithms that use traditional and a new stochastic state-space partitioning, the latter resulting in the minimum number of states. We then use them to solve the problem of active learning, that uses a knowledgeable teacher to generate samples as counterexamples to simulation equivalence queries. We show that the problem is undecidable in general, but that it becomes decidable under a suitable condition on the teacher which comes naturally from the way samples are generated from failed simulation checks. The latter problem is shown to be undecidable if we impose an additional condition on the learner to always conjecture a minimum state hypothesis. We therefore propose a semi-algorithm using stochastic partitions. Finally, we apply the proposed (semi-) algorithms to infer intermediate assumptions in an automated assume-guarantee verification framework for probabilistic systems.
Anvesh Komuravelli, Corina Pasareanu, Edmund M. Clarke
LICS1
2011 Analog circuit verification by statistical model checking
abstract
We show how statistical Model Checking can be used for verifying properties of analog circuits. As integrated circuit technologies scale down, manufacturing variations in devices make analog designs behave like stochastic systems. The problem of verifying stochastic systems is often difficult because of their large state space. Statistical Model Checking can be an efficient verification technique for stochastic systems. In this paper, we use sequential statistical techniques and model checking to verify properties of analog circuits in both the temporal and the frequency domain. In particular, randomly sampled system traces are sequentially generated by SPICE and passed to a trace checker to determine whether they satisfy a given specification, until the desired statistical strength is achieved.
Ying-Chih Wang, Anvesh Komuravelli, Paolo Zuliani, Edmund M. Clarke
ASP-DAC2
2011 Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces
abstract
Automated methods for bug localization for hardware designs typically work on the design implementation to root-cause a given bug. This paper presents a novel debugging approach where instead of using the design implementation in the debugging process, we use causal deduction using formal properties scattered across the design to locate the bug. This has two advantages, namely, (a) the reasoning takes place in the property space instead of the state space of the implementation, which enhances scalability, and (b) new properties can be added in hindsight to perform what-if analysis, which is less expensive than modifying the implementation for each alternative. Experimental results demonstrate the scalability of the approach in debugging designs with large property suites.
Anvesh Komuravelli, Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta
Asian Test Symposium1
2010 Analysis and verification of the HMGB1 signaling pathway
abstract
BACKGROUND: Recent studies have found that overexpression of the High-mobility group box-1 (HMGB1) protein, in conjunction with its receptors for advanced glycation end products (RAGEs) and toll-like receptors (TLRs), is associated with proliferation of various cancer types, including that of the breast and pancreatic. RESULTS: We have developed a rule-based model of crosstalk between the HMGB1 signaling pathway and other key cancer signaling pathways. The model has been simulated using both ordinary differential equations (ODEs) and discrete stochastic simulation. We have applied an automated verification technique, Statistical Model Checking, to validate interesting temporal properties of our model. CONCLUSIONS: Our simulations show that, if HMGB1 is overexpressed, then the oncoproteins CyclinD/E, which regulate cell proliferation, are overexpressed, while tumor suppressor proteins that regulate cell apoptosis (programmed cell death), such as p53, are repressed. Discrete, stochastic simulations show that p53 and MDM2 oscillations continue even after 10 hours, as observed by experiments. This property is not exhibited by the deterministic ODE simulation, for the chosen parameters. Moreover, the models also predict that mutations of RAS, ARF and P21 in the context of HMGB1 signaling can influence the cancer cell's fate - apoptosis or survival - through the crosstalk of different pathways.
Haijun Gong, Paolo Zuliani, Anvesh Komuravelli, James R. Faeder, Edmund M. Clarke
BMC Bioinform.3
2010 A static verification approach for architectural integration of mixed-signal integrated circuits
Rajdeep Mukhopadhyay, Anvesh Komuravelli, Pallab Dasgupta, Siddhartha Mukhopadhyay
Integr.2
2009 Exploring Polygonal Environments by Simple Robots with Faulty Combinatorial Vision
Anvesh Komuravelli, Matús Mihalák
SSS1
2009 Connectivity preserving transformations for higher dimensional binary images
Anvesh Komuravelli, Arijit Bishnu
Discret. Appl. Math.1
2008 Connectivity Preserving Voxel Transformation
Anvesh Komuravelli, Arijit Bishnu
IWCIA1