The rapid growth of LLM inference has exposed critical bottlenecks in GPU memory capacity and data movement efficiency. When GPU memory is exhausted, modern inference frameworks rely on GPUDirect Storage (GDS) with PCIe P2P transfers to stage data—such as KV caches and intermediate tensors—between GPU and NVMe-based storage. NVMe storage remains a significant performance bottleneck, with state-of-the-art enterprise PCIe Gen5 SSDs delivering only 14 GB/s sequential reads and 7 GB/s writes per drive. In this work, we evaluate a CXL memory expander equipped with an on-device DMA controller as a high-performance staging tier in GDS-style data paths. Although contemporary GPUs do not natively participate in the CXL protocol, our design works around this gap: the device-side DMA controller drives PCIe peer-to-peer (P2P) transfers directly against GPU HBM, while CXL is used only on the host side for capacity expansion and device management. We develop a custom NIXL backend plugin to enable benchmarking of GPU-to-expander data movement, and use NIXLBench to characterize transfer performance across transfer sizes and request parallelism configurations. The expander achieves 51 GB/s read bandwidth (~80% of the PCIe Gen5 ×16 peak) and 33 GB/s write bandwidth—utilizing a substantially larger fraction of the PCIe Gen5 ×16 interconnect than leading Gen5 NVMe SSDs achieve on the same interconnect generation. The remaining ~1.5× read/write gap is consistent with PCIe transaction completion semantics and leaves room for further write-side optimization. Multi-threaded descriptor submission, a routine capability of modern inference frameworks, additionally lowers the block size at which peak bandwidth is reached from 8 MB to 256 KB, sustaining high bandwidth for fine-grained LLM inference workloads such as KV cache updates.

Verification is a critical task in the development of correct computing systems. Simulation remains the predominantly used technique to identify design flaws, due to its scalability. However, simulation intrinsically suffers from low functional coverage, hence often fails to identify all design flaws. Formal verification (FV) is a promising approach to overcome the coverage limitations of simulation, due to its exhaustiveness - which enables it to identify intricate design flaws too complex to practically find using simulation. However, automated FV techniques have scalability drawbacks that limit the size of design components that can be formally verified. One of the key strengths of FV techniques is their use of symbolic reasoning, to efficiently explore a huge number of individual scenarios that would be intractable using simulation. When used in an incomplete manner, the scalability challenges of these algorithms are lessened, enabling efficient and relatively scalable semi-formal bug hunting. Nonetheless, to yield a robust industrial-strength solution, the individual components of such a system - many being heuristic - must be highly tuned, and integrated and orchestrated in an intricate manner. In this paper, we overview the various components useful in a scalable semi-formal search framework, introducing several novel powerful techniques and providing experimental data to illustrate the strengths, weaknesses, and complementary nature of the various techniques.

Generation of accurate IP power models requires determination of correct simulation conditions for the different input pins of the IP. Determining such a set of inputs for individual IP blocks in a design is expensive in cost and time, and is also highly error prone. Additionally, it is desirable to identify IP instances in a design, where these simulation conditions are not met. These are relevant problems in the context of modern day microprocessor designs, which are designed using a very large number of IPs, either developed in-house or sourced from external vendors. In this paper, we examine these problems in an industrial context and introduce FVCAG, a framework for enabling efficient and accurate power modelling. FVCAG enables a more thorough IP power modelling than that can be accomplished using current state of the art techniques. Experimental evaluation of the proposed framework on the standard cell library and macros used in the design of an industry class high performance microprocessor design demonstrates the accuracy and efficiency of proposed framework.

Verification benefits from removing logic that is not relevant for a proof. Techniques for doing this are known as localization abstraction. Abstraction is often performed by selecting a subset of gates to be included in the abstracted model; the signals feeding into this subset become unconstrained cut-points. In this paper, we propose several improvements to substantially increase the scalability of automated abstraction. In particular, we show how a better integration between the BMC engine and the SAT solver is achieved, resulting in a new hybrid abstraction engine, that is faster and uses less memory. This engine speeds up computation by constant propagation and circuit-based structural hashing while collecting UNSAT cores for the intermediate proofs in terms of a subset of the original variables. Experimental results show improvements in the abstraction depth and size.

The verification of embedded software has become an important subject over the last years. This work presents a new semiformal verification approach called SofTPaDS. It combines assertion-based and symbolic simulation approaches for the verification of embedded software with hardware dependencies. SofTPaDS shows to be more efficient than the software model checkers in order to trace deep state spaces and improves the state coverage relative to a simulation-based verification tool. We have successfully applied our approach to an industrial automotive embedded software.

The amount of software in embedded systems has increased significantly over the last years and, therefore, the verification of embedded software is of fundamental importance. One of the main problems in embedded software is to verify variables and functions based on temporal properties. Formal property verification using model checker often suffers from the state space explosion problem when a large software design is considered. In this paper, we propose two new approaches to integrate assertions in the verification of embedded software using simulation-based verification. Firstly, we extended a SystemC hardware temporal checker with interfaces in order to monitor the embedded software variables and functions that are stored in a microprocessor memory model. Secondly, we derived a SystemC model from the original C program in order to integrate directly with the SystemC temporal checker. We performed a case study on an embedded software from automotive industry which is responsible for controlling read and write requests to a non-volatile memory.

Symbolic property verification is an increasingly popular debugging method based on Binary Decision Diagrams (BDDs). The lack of optimization of the state space search is often responsible for the excessive growth of the BDDs. In this paper we present an accelerated symbolic property verification by means of a new guiding technique that automatically finds the set of interesting variables by exploiting the property and the transition relation of a design. Our property based state space guiding can substantially speed up the verification process. The heuristic picks up the interesting state or the input variables automatically and utilizes them in guiding the state space traversal. This guiding approach is a novel one as it is automatic, efficient and stable for fast falsification. Furthermore it does not degrade as much for full validation.