This demonstration presents an energy and area efficient Reconfigurable Cryptographic Accelerator (RCA) SoC for secure communication in IoT devices. Built on a ZYNQ-7000 development board, the platform supports multiple block ciphers (DES, AES, SM4) and Hash functions (SHA-1, SHA-2, SM3). Users can follow prompts on the OLED screen to select the cryptographic algorithm via buttons and input data through a keyboard or choose large text files from SD card. The ARM Core and accelerator execute the cryptographic operation simultaneously, and energy efficiency is calculated based on power and computing time, showcasing the improved computing speed and energy efficiency of the proposed accelerator.

In many intelligent edge applications involving Autonomous Mobile Robots (AMRs), efficient and real-time localization and mapping is a fundamental issue. Extended Kalman Filter Simultaneous Localization and Mapping (EKFSLAM) algorithm is a classic and successful solution to realize localization and mapping, while it is computationally intensive and poses a challenge for real-time tasks in small and micro robots. To address this issue, this work proposes an energy-efficient, highframe-rate, and reconfigurable EKF-SLAM processor. Firstly, a heterogeneous dual-core architecture is proposed to enable full acceleration of both matrix operations and nonlinear calculations in EKF-SLAM at the hardware architecture level. Secondly, a Reconfigurable Matrix Accelerator (RMA) and Reconfigurable Nonlinear Accelerator (RNA) are proposed to maximize data reuse and support diverse nonlinear functions at the data flow level. Thirdly, a data property-aware strategy is proposed at the data property level, which exploits matrix symmetry, sparsity, and dependency to reduce storage significantly and eliminate redundant computations. FPGA validation results show that the proposed design can achieve a frame rate of 774 fps and an energy efficiency of 0.66 mJ/frame, when performing mapping processes involving 60 landmarks at 100 MHz.

Many applications of machine learning (ML) have been integrated into edge devices with their low communication latency. In edge computation, the reprocessing of redundant data results in considerable energy waste. The prior research utilized a digital-delta-digital-sigma computing-in-memory (CIM) scheme to mitigate this redundancy. However, the 7-bit LSB-first ADC resulting from the near-zero-mean output distribution led to excessive area and latency overhead. The following digital adder further induced power consumption and latency. We propose a digital-delta-analog-sigma CIM macro incorporating an analog sigma converter (SC) for edge computation, involving a switch-capacitor integrator with a floating inverter amplifier (FIA) and a quantizer. The increased analog swing of the sigma integrator leads to the expanded output distribution, thereby maintaining comparable accuracy with a relaxed quantizer resolution. The simulation demonstrates that our strategy contributes to a 57.5% reduction in latency, a resolution decrease of 2 bits, and better energy efficiency. These improvements can potentially enhance energy efficiency and computational speed in edge computation devices.