The post-silicon integrated circuits (IC) testing is a very expensive process, especially in automotive industry where chip functionality has to be guaranteed by verifying multiple electrical parameters over a wide range of operating conditions. However, some costs can be avoided by reducing the amount of redundant tests, as certain parameters may exhibit a predictable behavior on the operating conditions variation. This paper presents a comparison between three approaches that use temperature parameters behavior for reducing the number of IC tests. The methods are tested on a production dataset consisting of 25 parameters and 300000 chips, results showing that the best method saves approximately 12 % of the measurements.

Analog and Mixed Signal circuit sizing with large-scale parameters requires a lot of simulations, especially in non-linear topology where large-signal analysis is a need. Reducing the number of simulations and in general the total design cycle time, is the main objective for optimal sizing of complicated circuits. In this work a circuit sizing automated design methodology is presented using the hybrid dual annealing and Nelder–Mead algorithm, significantly reducing the design cycle time and the required number of transient simulations. A customized hybrid algorithm environment using Dual Annealing and Nelder–Mead is developed where the optimization process is divided into different optimization sub-steps. The proposed hybrid algorithm based method achieves rapid convergence to the needed circuit performance specification. It uses combinations of direct search algorithms to separate metric evaluation accelerating the performance specifications convergence speed in a large parameter space. A complicated non-linear topology like a product level low-dropout (LDO) regulator, in 180 nm process node, with 30 parameters is used as the circuit vehicle to verify the proposed methodology. The sizing process converged with less than 1700 simulations having as input just the circuit schematic with no prior sizing knowledge. Sub optimization is also performed focused on each analysis type - DC, AC and transient, with a focus on reducing the number of transient simulations. The proposed combined algorithm method achieved 31 % faster convergence speed compared to the state-of-the-art methods and handles efficiently each simulation analysis. • Analog circuits have metrics that in general need different simulation types for evaluation. A number of combinations of algorithms are proposed to optimize different sub-stages of the process. • A large LDO circuit is used as a base for the demonstration and comparison of the methodologies, with 30 parameters and 10 performance metrics. • Significant number of transient analysis simulations is reduced (31%), keeping the result within the error limits, using the best performing hybrid algorithms that include Nelder–Mead, Dual Annealing, NSGA-II, etc.

Automated circuit sizing using Artificial Intelligence is a rapidly increasing area of interest, primarily thanks to its potential to accelerate product time-to-market and enhance employee satisfaction. A host of methods, rooted in different fundamental research philosophies, have been devised for this class of problems. While some of them perform well in terms of convergence speed , robustness has generally been given less attention. In this study we propose a novel automatic circuit sizing framework called Evolutionary Bayesian Optimization (EBO). It is a hybrid method combining the strengths of evolutionary computation techniques and Bayesian Optimization. EBO takes full advantage of parallel simulation infrastructure, by inherently using large batches of simulations. Our method is especially designed for multi-objective problems. Thus, it can optimize a large variety of circuits without the need of constructing figure of merit functions. Moreover, the strong emphasis on exploring the high-dimensional space of design variables ensures that EBO is robust and reliable across varying levels of problem complexity. We compare our framework with two state-of-the-art methods having different underlying philosophies and with arguably the most promising multi-objective evolutionary algorithm for this class of problems on four circuits: two proprietary voltage regulators, an open-source voltage regulator, and an open-source operational amplifier . The results show that EBO is superior to the other considered methods with regard to convergence speed and robustness. Generally, it can save between 30% and 70% circuit simulations compared to the next best performing method. Furthermore, EBO is the only method that finds circuit configurations that meet the specifications for all the considered circuits.

This paper introduces several solutions for multivariate extension of a previously designed single response adaptive pre-silicon integrated circuit verification approach employing machine learning algorithms. These techniques aim to achieve the most accurate identification of worst-case circuit behavior through simultaneously modeling multiple electrical parameters (EP). The effectiveness of the proposed methods was validated through extensive testing on a large and diverse set of synthetic test functions that intend to replicate the behavior of real circuits. The algorithms consistency and accuracy are also validated on a real Low Dropout Voltage Regulator (LDO) circuit.

Circuit sizing for designs with many design variables and responses is a complex task that requires highly experienced and creative designers to invest precious time in trial and error, routine work. In addition, sizing the circuit while also taking into account PVT (process, voltage, temperature) variation corners increases the complexity further. To simplify such tasks, designers select the most unfavorable PVT corner in advance (leveraging their expertise), perform circuit sizing for this condition, and finally verify the resulting design in all PVT corners. This procedure might generate designs that fail the specifications in other PVT corners leading to more design-verification iterative loops. Recent years brought machine learning (ML) and optimization techniques to the field of circuit design, with evolutionary algorithms and Bayesian models showing good results for automated circuit sizing. However, these methods can still require an unfeasibly large number of simulations, especially if taking into account several PVT corners. In this context, we introduce a methodology that uses surrogate ML models to perform PVT variation-aware circuit sizing. We propose to dynamically select the worst PVT corners and take them into account when sizing the circuit. In addition, we explore the best ways to model process corners with Gaussian Processes, leading to more than 10x improvements for such surrogate models. We evaluate the proposed corner management method on two voltage regulators showing different levels of complexity and highlight that it enables finding feasible solutions 2x faster when compared to baseline algorithms which optimize in all PVT corners. In addition, the quality and diversity of the proposed solutions are significantly higher by one to three orders of magnitude in terms of population hypervolume.

Manual sizing of analog circuit specifications has become challenging owing to their ever-increasing complexity. Especially for innovative, large-scale circuit designs with numerous design variables, operating conditions, and conflicting objectives to optimize, analog designers must run time-consuming simulations for several weeks to find the optimum configuration. Recently, machine learning and optimization techniques have been applied in the field of analog circuit design, wherein evolutionary algorithms and Bayesian models have shown good results for circuit sizing tasks. In this context, we introduce multi-objective optimization based on differential evolution and Bayesian inference (MODEBI)—a design optimization method based on generalized differential evolution 3 (GDE3) and Gaussian processes (GPs). The proposed method can perform sizing for complex circuits that require optimization of many design variables and conflicting objectives. Although state-of-the-art methods reduce multi-objective problems to single-objective optimization and potentially induce a priori bias, the proposed method searches directly over the multi-objective space using Pareto dominance and ensures that designers are provided with diverse solutions to choose from. To reduce optimization time, we propose using GPs to model the circuit and employing this surrogate model to preselect candidates. However, this results in a more complex offspring selection process, and the diversity in population survival must be specifically addressed. This paper proposes several solutions to these problems, resulting in multiple MODEBI variations. To the best of our knowledge, this is the first method that specifically addresses solution diversity and simultaneously focuses on minimizing the number of simulations required to obtain feasible configurations. The evaluation performed on two voltage regulators with different complexity levels showed that the proposed offspring selection method and survival policy can obtain highly diverse feasible solutions considerably faster than GDE3 or Bayesian optimization-based algorithms.

There is a consistent dependence between integrated circuits (ICs) performance parameters and manufacturing process variations and capturing it at an early development phase represents a major ongoing topic in the semiconductor industry. Typically, this is addressed by the means of Monte Carlo (MC) simulations, where the device model parameters are randomly instantiated according to the technology variations based on a predefined nominal process. Thus, the resulted simulation data can only capture the effect of these variations. This offers little or no insight on the performance’s sensitivities to specific process variations or on the effect of altered statistical technology properties, as it may be the case of process drift or fab-to-fab migration. This article proposes a methodology for modeling the dependency of the device performances (i.e., electrical parameters—EPs) with the influential technology parameters (i.e., process control monitor parameters—PCMs), at an early stage (preSilicon). Using a set of standard MC co-simulations of PCM structures and the circuit schematics (to maintain consistent process variation), it employs a feature selection step to choose the influential PCMs and it trains a machine learning regression algorithm. Both are wrapped up in a Bayesian optimization (BO) framework to find the optimal feature set and the regression hyperparameters. The obtained regression model can explain the functional dependency of the EP on the influential PCMs. Thus, it directly enables sensitivity analysis (SA) to process variation and parametric yield prediction of the IC, as it will be illustrated for the case of an experimental Infineon Technologies product.

This paper proposes a pole-placement method for tuning the discrete PID control of a DC-DC Buck converter that ensure specific time-domain performances when a step disturbance in the input voltage or load is applied. The control is also designed to reduce steady-state oscillations caused by the digital implementation nonlinearities of the control loop. The effectiveness of the method is verified on both simulation and experimental levels.

This paper proposes a method for speeding-up the verification process of integrated circuits, featuring waveform clustering of circuit response signals. The main objective is to automatically separate the signals into distinct groups that potentially exhibit visual similarities in order to aid the visual inspection/verification. As a first step, the proposed method extracts SIFT-like features by finding stable points of the signal over the scale space and computing robust descriptors able to describe their neighborhood. The resulted descriptors are quantized in order to be used in the clustering process as bag-of-words histograms. We demonstrate the validity of our method on a circuit waveform database containing several thousands of signals belonging to ten electrical tests.

Although many efforts have been made in the last decade to enhance the speech and language resources for Romanian, this language is still considered under-resourced. While for many other languages there are large speech corpora available for research and commercial applications, for Romanian language the largest publicly available corpus to date comprises less than 50 hours of speech. In this context, Speech and Dialogue research group releases Read Speech Corpus (RSC) – a Romanian speech corpus developed in-house, comprising 100 hours of speech recordings from 164 different speakers. The paper describes the development of the corpus and presents baseline automatic speech recognition (ASR) results using state-of-the-art ASR technology: Kaldi speech recognition toolkit.

This paper proposes a method for explanation of the lifetime variation of power devices using data from different test stages. Understanding the lifetime variation is very useful in qualification, as well as in the characterization process, in order to improve the robustness of the power devices or to estimate more accurately the minimum guaranteed lifetime. Moreover, it helps design engineers better understand the root causes of the lifetime variation and use this knowledge to improve the performances of new power devices. In the proposed methodology, the variation of the lifetime is explained by the electrical parameters, measured before the stress-test. The Sensitivity Analysis presented here has the advantage of being simple and fast. It can be applied even when the number of test-runs is less than the number of factors. Moreover, it reveals not only linear correlations, but also quadratic effects and 2nd and 3rd order interactions. Eventually, the method provides the top of the most relevant electrical parameters which explain the lifetime variation. The validation of this approach has shown that 72% of the lifetime variation can be explained by the initial values of 5 electrical parameters.

The standard metrics for integrated circuits' analysis and characterization in production processes usually assume that the process under investigation is characterized by a normal distribution. However, the data met in practice are not always normal and the yield estimates may be inaccurate. In this paper we propose estimating the yield by using a distribution fitting flow. The selected distribution types proved to estimate more accurate yields, with lower variance of the estimates. The distribution models proved to be a reliable tool also for integrated circuits' characterization in terms of specification limits' determination.

The paper proposes a methodology for lifetime estimation of power devices at given applications operating conditions. The active cycling of power devices requires huge testing-time, because the process cannot be accelerated. For this reason, most often, the manufacturers provide information about the lifetime of power devices only for a few specific operating conditions. Most of the current methods are based on the junction temperature swing, which is very difficult to be measured or estimated. Instead, we propose an approach that, based on a few measurements of lifetime at given ambient temperatures, load currents and repetitive energies, is able to make lifetime prediction at any other set of operating conditions. The validation of the method was done by performing lifetime predictions in other operating conditions than those used for fitting the prediction function (metamodel) and it has shown a maximum relative error of 20%. With the proposed methodology, lifetime estimations of power devices can be made in the space of applications operating conditions, using optimal testing resources.

In this paper, we present the task and describe the main findings of the 2014 “Query-by-Example Speech Search Task” (QUESST) evaluation. The purpose of QUESST was to perform language independent search of spoken queries on spoken documents, while targeting languages or acoustic conditions for which very few speech resources are available. This evaluation investigated for the first time the performance of query-by-example search against morphological and morpho-syntactic variability, requiring participants to match variants of a spoken query in several languages of different morphological complexity. Another novelty is the use of the normalized cross entropy cost (Cnxe) as the primary performance metric, keeping Term-Weighted Value (TWV) as a secondary metric for comparison with previous evaluations. After analyzing the most competitive submissions (by five teams), we find that, although low-level “pattern matching” approaches provide the best performance for “exact” matches, “symbolic” approaches working on higher-level representations seem to perform better in more complex settings, such as matching morphological variants. Finally, optimizing the output scores for Cnxe seems to generate systems that are more robust to differences in the operating point and that also perform well in terms of TWV, whereas the opposite might not be always true.

As systems and electrical and electronic devices are becoming more and more complex, the number of requirements is increased accordingly. Therefore, the organization, the processing and the verification of requirements has become a necessity. In automotive applications, this necessity is more pronounced because of the safety regulations imposed by authorities. Semi-formal representation is an approach that helps making the requirements more understandable and rigorous. In particular, SysML has proved to have the capabilities to represent requirements, structure and behaviour of systems and devices in a diagram-based fashion, enabling the linking different elements that define the composition and the functionalities of the desired product. While for software systems and digital hardware it has been applied successfully, very little work has yet been done for analogue and analogue-mixed signal devices. This is mainly because of the particular behaviour of such devices and the continuous quantities related to them. In this paper, we describe the modelling of requirements for an electronic power switch in SysML. We show that the description of the requirements for analogue devices is possible and emphasize its utility in a real scenario.

As part of the MediaEval 2013 benchmark evaluation campaign, the objective of the Spoken Web Search (SWS) task was to perform Query-by-Example Spoken Term Detection (QbESTD) using audio queries in a low-resource setting. After two successful editions and a continuously growing interest in the scientific community, a special effort was made in SWS 2013 to prepare a challenging database, including speech in 9 different languages with diverse environment and channel conditions. In this paper, first we describe the database and the performance metrics. Then, we briefly review the algorithmic approaches followed by participants and present and discuss the obtained performances, which demonstrate the feasibility of the proposed task, even under such challenging conditions (multiple languages and unconstrained acoustic conditions). Finally, we analyze the fusion of the top-performing systems, which achieved a 30% relative improvement over the best single system in the evaluation, proving that a variety of approaches can be effectively combined to bring complementary information in the search for queries.

This study investigates the use of machine translated text for ASR domain adaptation. The proposed methodology is applicable when domain-specific data is available in language X only, whereas the goal is to develop a domain-specific system in language Y. Two semi-supervised methods are introduced and compared with a fully unsupervised approach, which represents the baseline. While both unsupervised and semi-supervised approaches allow to quickly develop an accurate domain-specific ASR system, the semi-supervised approaches overpass the unsupervised one by 10% to 29% relative, depending on the amount of human post-processed data available. An in-depth analysis, to explain how the machine translated text improves the performance of the domain-specific ASR, is also given at the end of this paper.