Demo Data from EDBT 2026 / reviewers in the wild / expert
Keyong Zhou
dblp:11/11470
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2020
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Databases, data management, data science and information retrieval · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Databases, data mining, and information retrieval
1 paper |
Query processing and optimization · 50% Database system architecture and tuning · 50% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 81% Processor architecture and microarchitecture · 19% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Query processing and optimization
query result caching |
0.4 | 1 | 2020 | Maxson: Reduce Duplicate Parsing Overhead on Raw Data · ICDE 2020 |
Performance modeling and evaluation
simulation |
0.1 | 1 | 2012 | Transformer: a functional-driven cycle-accurate multicore simulator · DAC 2012 |
Performance modeling and evaluation › simulation › architectural simulation
full-system simulation |
0.0 | 1 | 2012 | Transformer: a functional-driven cycle-accurate multicore simulator · DAC 2012 |
Processor architecture and microarchitecture
multicore design |
0.0 | 1 | 2012 | Transformer: a functional-driven cycle-accurate multicore simulator · DAC 2012 |
Methods — techniques the papers use, named apart from their topics
conditional random field · 0.4LSTM · 0.4parallelization · 0.1loosely-coupled functional and timing models · 0.1functional-driven simulation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Maxson: Reduce Duplicate Parsing Overhead on Raw DataabstractJSON is a very popular data format in many applications in Web and enterprise. Recently, many data analytical systems support the loading and querying JSON data. However, JSON parsing can be costly, which dominates the execution time of querying JSON data. Many previous studies focus on building efficient parsers to reduce this parsing cost, and little work has been done on how to reduce the occurrences of parsing. In this paper, we start with a study with a real production workload in Alibaba, which consists of over 3 million queries on JSON. Our study reveals significant temporal and spatial correlations among those queries, which result in massive redundant parsing operations among queries. Instead of repetitively parsing the JSON data, we propose to develop a cache system named Maxson for caching the JSON query results (the values evaluated from JSONPath) for reuse. Specifically, we develop effective machine learning-based predictor with combining LSTM (long shortterm memory) and CRF (conditional random field) to determine the JSONPaths to cache given the space budget. We have implemented Maxson on top of SparkSQL. We experimentally evaluate Maxson and show that 1) Maxson is able to eliminate the most of duplicate JSON parsing overhead, 2) Maxson improves end-to-end workload performance by 1.5-6.5×. Xuanhua Shi, Hong Huang 0001, Hai Jin 0001, Huan Shen, Yongluan Zhou, Bingsheng He, Ruibo Li, Keyong Zhou |
ICDE | 10 |
| 2012 | Transformer: a functional-driven cycle-accurate multicore simulatorabstractFull-system simulators are extremely useful in evaluating design alternatives for multicore. However, state-of-the-art multicore simulators either lack good extensibility due to their tightly-coupled design between functional model (FM) and timing model (TM), or cannot guarantee cycle-accuracy. This paper conducts a comprehensive study on factors affecting cycle-accuracy and uncovers several contributing factors ignored before. Based on the study, we propose a loosely-coupled functional-driven full-system simulator for multicore, namely Transformer. To ensure extensibility and cycle-accuracy, Transformer leverages an architecture-independent interface between FM and TM and uses a lightweight scheme to detect and recover from execution divergence between FM and TM. Based on Transformer, a graduate student only needs to write about 180 lines of code and takes about two months to extend an X86 functional model (QEMU) in Transformer. Moreover, the loosely-coupled design also removes the complex interaction between FM and TM and opens the opportunity to parallelize FM and TM to improve performance. Experimental results show that Transformer achieves an average of 8.4% speedup over GEMS while guaranteeing the cycle-accuracy. A further parallelization between FM and TM leads to 35.3% speedup. Zhenman Fang, Qinghao Min, Keyong Zhou, Yibin Hu, Haibo Chen 0001, Jian Li 0059, Binyu Zang |
DAC | 3 |