In this paper, we propose a method to directly describe the RTL structure of a pipelined RISC- V processor with cache, memory management unit (MMD) and AXI bus interface using C++ language. This processor C++ model serves as a near cycle-accurate simulation model of the RISC- V core, while our C2RTL framework translates the processor C++ model into cycle-accurate RTL description in Verilog-HDL and RTL-equivalent C model. Our design methodology is unique compared to other existing methodologies since both the simulation model and the RTL model are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor which runs Linux OS on an FPGA board as well as significantly short simulation time of the original C++ processor model and RTL-equivalent C model compared to commercial RTL simulator.

Gradient Boosted Tree is most effective and standard machine learning algorithm in many fields especially with various type of tabular dataset. Besides, recent industry field and robotics field require high-speed, power efficient and real-time training with enormous data. FPGA is effective device which enable custom domain specific approach to give acceleration as well as power efficiency. We introduce a scalable full hardware implementation of Gradient Boosted Tree training with high performance and flexibility of hyper parameterization. Experimental work shows that our hardware implementation achieved 11–33 times faster than state-of-art GPU acceleration even with small gates and low power FPGA device.

Autonomous underwater vehicles (AUVs), unmanned underwater vehicles, are cheaper to operate than remotely operated vehicles (ROVs), since an AUV does not require a trained human operator to control. As a result, in this paper, we propose the pipeline tracking algorithm using sequences of the forward-looking sonar (FLS) images installed on a preprogram AUV. The FLS is more suitable to be used in the subsurface environment than an optical camera due to the limited visibility and floating particles in the sub-sea surface environment. In our work we first employed the speckle noise reduction to the FLS images. Then, we applied the level-set method (LSM) to extract a pipeline boundary in each frame. Lastly, the post-processing step was designed to link the unconnected segments together to from a complete pipeline. Our algorithm can perform the segmentation and tracking with more than 85% accuracy.

This paper presents an Application Specific Instruction set Processor (ASIP) for object detection using AdaBoost-based learning algorithm with Haar-like features as weak classifiers. In the proposed ASIP, Single Instruction Multiple Data (SIMD) architecture is adopted for fully exploiting data-level parallelism inherent to the target algorithm.With adding pipeline stages, application-specific registers and custom instructions, AdaBoost algorithm is accelerated by a factor of 13.7× compared to baseline processor. Furthermore, the results show an advantage of the proposed architecture in terms of chip area efficiency while maintain a reliable detection accuracy and achieve real-time object detection at 32fps on VGA video.

In multiprocessor systems, low-latency synchronization is extremely important to effectively exploit fine-grain data parallelism and improve overall performance. This brief presents an efficient synchronization for embedded distributed multiprocessors. The proposed solution works in a completely decentralized request-response manner via explicit message exchange among the processing elements. Scalable lock and barrier synchronization algorithms, which are derived from the inherent distributed characteristics of the underlying architecture, are proposed to enable fair, orderly, and contention-free synchronization. We implement the proposed synchronization model in a distributed 32-core architecture with a commercial cycle-accurate SystemC simulation platform. Experimental results that show our proposed approach achieves ultralow synchronization latency and almost ideal scalability when the core count scales.

This paper presents a distributed synchronization architecture for message-passing based embedded multiprocessors. The proposed solution effectively realizes the lock and barrier protocols in a completely decentralized manner without traffic contention. We implement the proposed mechanism using application-specific instruction-set processor (ASIP) techniques to speed up the message passing and handling. Experimental results show the proposed synchronization achieves ultra-low latency and almost ideal scalability when the number of processors increases.

The traditional land cover mapping (LCM) algorithms assume that images are perfectly registered. In practice, this assumption may not always be valid since these images may be acquired from different sensor platforms, or at different time which may suffer small variations in platform flight paths. As a result, it is imperative to incorporate the registration error into the land cover mapping algorithm. In this paper, we propose a joint LCM and image registration algorithm under the Markov random field model. Here, the expectation-maximization algorithm is employed to search for the optimum LCM as well as the map parameters. Our result shows that the proposed MRF-Based approach can increase the accuracies of the classification maps as well as the map parameter estimation.

This paper summarizes a special session on multi-core/multi-processor system-on-chip (MPSoC) programming challenges. Wireless multimedia terminals are among the key drivers for MPSoC platform evolution. Heterogeneous multi-processor architectures achieve high performance and can lead to a significant reduction in energy consumption for this class of applications. However, just designing energy efficient hardware is not enough. Programming models and tools for efficient MPSoC programming are equally important to ensure optimum platform utilization. Unfortunately, this discipline is still in its infancy, which endangers the return on investment for MPSoC architecture designs. On one hand there is a need for maintaining and gradually porting a large amount of legacy code to MPSoCs. On the other hand, special C language extensions for parallel programming as well as adapted process network programming models provide a great opportunity to completely rethink the traditional sequential programming paradigm for sake of higher efficiency and productivity. MPSoC programming is more than just code parallelisation, though. Besides energy efficiency, limited and specialized processing resources, and real-time constraints also growing software complexity and mapping of simultaneous applications need to be taken into account. We analyze the programming methodology requirements for heterogeneous MPSoC platforms and outline new approaches.

While Multiprocessor System-On-Chips (MPSoCs) are becoming widely adopted in embedded systems, there is a strong need for methodologies that quickly and accurately estimate performance of such complex systems. In this paper, we present a novel method for accurately estimating the cycle counts of parameterized MPSoC architectures through workload simulation driven by program execution traces encoded in the form of branch bitstreams. Experimental results show that the proposed method delivers a speedup factor of 70.15 to 238.58 against the instruction-set simulator based method while achieving high cycle accuracy whose estimation error ranges between 0.016% and 0.459%.

In the past few years, MPSoC has become the most popular solution for embedded computing. However, the challenge of programming MPSoCs also comes as the biggest side-effect of the solution. Especially, when designers have to face the legacy C code accumulated through the years, the tool support is mostly unsatisfactory. In this paper, we propose an integrated framework, MAPS, which aims at parallelizing C applications for MPSoC platforms. It extracts coarsegrained parallelism on a novel granularity level. A set of tools have been developed for the framework. We will introduce the major components and their functionalities. Two case studies will be given, which demonstrate the use of MAPS on two different kinds of applications. In both cases the proposed framework helps the programmer to extract parallelism efficiently.

In this paper, we introduce our work on the chip design of a new FPGA chip for high-performance bit-serial pipeline datapath which is customized both in the logic architecture and routing architecture. The chip consists of 200k transistors on 3.5 mm square substrate (excluding the IO pad area) using 0.5 /spl mu/ 2-metal process technology. The estimated clock frequency is 156 MHz.

In this paper, we present our work on the design of a new FPGA architecture targeted for high-performance bit-serial pipeline datapath. Bit-parallel systems introduce large routing area overhead which is especially critical in using FPGAs, where the device utilization, and operation frequency become low because of large routing penalty. Here we propose a new FPGA architecture for high-performance bit-serial pipeline datapaths, which are very efficient in routing. Also, we refine our LUT architecture in order to efficiently implement shift registers which are required in large numbers in some bit-serial designs. Modified lookup table have two modes, combinatorial logic and shift register. Bit-serial datapath can be implemented on less number of CLBs.

No abstract available.

In this paper, we present our datapath synthesis and layout tools which are targeted toward large-scale configurable systems with the logic capacity of up to millions of gates which consists of an easy design entry using C++, customized bit-serial circuit library for SRAM-based FPGAs, bit-serial pipeline circuit generator, and a circuit partitioner.

Developing applications for a large-scale configurable system composed of state-of-the-art FPGA technology is a grand challenge. FPGAs are inherently resource limited devices in terms of logic, routing, and IO. Without a careful circuit implementation strategy, one would waste a large portion of the potential capacity of the configurable hardware. Also, high-level design entry support is essential for such large-scale hardware. A C++ design tool has been implemented which maps the computational algorithms onto bit-serial pipeline networks which exhibit high performance and maximize the device utilization of each FPGA. With this tool, the designer is able to develop applications in a very short time, and also is able to try out different algorithm implementations easily to see the trade-offs in terms of performance and hardware size instantaneously. Based on this C++ design tool, a number of DSP applications such as 1D and 2D filters, adaptive filters, Inverse Discrete Cosine Transform, and digital neural networks were designed.

Field�programmable hardware exhibits a new trend to� wards computation�intensive applications. The basic idea is to completely customize the hardware architec�