The primary purpose of this work is to automate selection of key attributes of a test data compression environment such as Embedded Deterministic Test, the first commercial test compression product. Given a test compression setup, the main objective of the proposed approach is to quickly estimate the expected test pattern count, test data volume, and the resultant test application time within the framework of the actual test compression flow when using ATPG-produced test cubes. This way one can mimic a process of test cube merging and anticipate compressibility of the resultant test patterns without resorting to CPU-intensive ATPG runs and solvers of linear equations. The obtained results, reported herein, are compared with actual stuck-at fault test patterns generated by a commercial test compression tool for several industrial designs in order to validate the proposed model. This allows a final tuning of the new scheme to arrive with a fast and accurate test compression advisement method. It can be used, prior to further steps, to devise the key elements of a test compression ecosystem such as the number of input channels and the size of on-chip test data decompressor.

On-chip test data decompressors [ 1 ] are the very first devices that have had deployed ring generators [ 2 , 3 ] – high performance linear feedback shift registers (LFSRs) – that quickly proved themselves as versatile solutions capable of outperforming traditional schemes through an unmatched speed of operations and layout-friendly structures [ 4 ]. Given a characteristic (feedback) polynomial, ring generators feature smaller internal fan-outs, shorter propagation paths, and simpler circuit layout and routing than popular and commonly used Fibonacci or Galois LFSRs [ 5 , 6 ] whose long irregular feedback paths may limit the operating speed, cause frequency degradation, and may take up a fair amount of silicon area, especially for polynomials with a large number of terms [ 7 ]. Figure 1 recalls a basic architecture of a 32-bit ring generator with a primitive polynomial h ( x ) = x 32 + x 28 + x 23 + x 20 + x 17 + x 12 + x 8 + x 4 + 1, which causes this ring generator to go through all possible 2 32 – 1 nonzero values before returning to a seed state. Typically, its structure can be created by forming a ring counter, and then by adding feedback taps which correspond to successive terms of a characteristic polynomial. A feedback loop associated with tap x k is made up from k adjacent flip-flops, beginning with the leftmost ones, as shown in the figure. Note that two feedback nets cannot cross each other [ 2 ]. If one uses an appropriate characteristic polynomial, then a ring generator may assume a regular ladder-like structure. An extensive collection of such primitive polynomials is available in [ 8 ]. Since a subset of k adjacent flip-flops can be chosen in different ways as long as the resultant feedback line does not cross any other feedback line, the ring generators offer an appreciable degree of flexibility in shaping their structures.

Nonlinear feedback shift registers (NLFSRs) are well-positioned to play the key role in securing variety of digital ecosystems. They have already been deployed as major building blocks of several hardware stream ciphers, and are expected to become an essential part of hardware roots of trust that protect integrated circuits (ICs) against hardware security threats and mitigate risks associated with an unauthorized access and usage of ICs. In this article, we present two new sets of Galois NLFSRs with maximum and near maximum prime periods, respectively. All reported registers have been identified by virtue of an FPGA-based engine running in parallel around 8000 search processes. This article provides a detailed description of metrics used to characterize output sequences produced by NLFSRs, such as the number of n-tuples each output sequence is comprised of, linear complexity of output sequences, and the total number of different maximum-length sequences obtained by means of simple linear filters driven by the examined registers. This article is accompanied by tables listing all found and never presented before NLFSRs, altogether with their architectural details and the corresponding metrics.

With the biennial doubling of the number of transistors in a given area of silicon, contemporary integrated circuits (IC) are forging more and more often and will continue to forge complex system-on-chip (SoC) designs. Their equally complex manufacturing and in-system tests are now carried out through top-level test data delivery nets that enable fast streaming of test data to, from, and throughout a chip. However, it is essential to apply restrictions mitigating risks associated with unauthorized access and usage of SoCs as well as to protect the test infrastructure against hardware security threats, and thus to prevent leakage of secret information or other sensitive assets while tests are carried out. Existing security IP cores raise concerns related to their complexity in terms of area footprint, performance, power, impact on an SoC integration flow, and testability. This paper presents simple and lightweight, yet effective and scalable, test data stream ciphers (SCs) that can be used to encrypt and decrypt test data employed in tests of SoCs and delivered via Streaming Scan Network (SSN) – a new packetized test data network. A single cipher is comprised of three Galois nonlinear feedback shift registers working in tandem to yield a large number of parallel, cryptographically secure pseudorandom keystreams. A comprehensive evaluation, including NIST statistical test suits, show high efficiency of the proposed ciphers, and is reported herein.

Additive stream ciphers (SCs) play a host of roles in securing variety of digital ecosystems. In particular, they can encrypt and decrypt test data used in manufacturing and in-system tests of digital integrated circuits (ICs). In this capacity, SCs have become an essential part of instruments that protect ICs against hardware security threats and mitigate risks associated with an unauthorized access and usage of ICs, possibly due to scan chains. However, many IC vendors keep raising concerns attributable to the complexity of existing SCs in terms of area overhead, performance, impact on a design flow, and testability. Here is where this work comes in. It introduces a simple and lightweight, yet effective and scalable, test data stream cipher Lancet developed for the Streaming Scan Network (SSN) technology to decrypt and encrypt the content of the IJTAG communication and the SSN bus. It builds on a hybrid ring generator working in tandem with two nonlinear Galois feedback shift registers to yield a large number of parallel, cryptographically secure pseudorandom keystreams. A comprehensive evaluation, including NIST test suits, show the efficiency of the proposed cipher, and is reported herein.

Recently the semiconductor industry has been alerted by hyperscaler companies reporting impact of field errors in megascale datacenters. They tend to be elusive and very difficult to detect until they affect a particular application several days or months after the IC has been deployed in a fleet. Although the cause of such errors can be manifold, ranging from test escapes and design marginalities to design bugs, there is a consensus across the industry that they usually can be traced back to timing-related issues, as the performance of transistors changes over time or at certain environmental conditions while running specific software workloads. While there is ongoing work to study some of those defects and to explore techniques preventing such post-manufacturing test escapes, it also highlights the need for IC monitoring so that such defects are detected in the field, thereby reducing application failures. The paper demonstrates a successful application of the Streaming Scan Network technology to run in-fleet deterministic scan test on an ultralarge industrial multi-chiplet design at Amazon Web Services (AWS) cloud computing platform. One of the key advantages of the presented technology is its ability to use the same infrastructure to perform both manufacturing and in-field tests. A silicon implementation along with test power analysis are also presented.

Protection of integrated circuits (ICs) against hardware security threats has been tackled by many schemes proposed to mitigate risks associated with an unauthorized access and usage of ICs in general, and intellectual property (IP) cores in particular. Typically, this is accomplished by virtue of hardware roots of trust whose crucial security primitives entail cryptographic hash functions. They provide data integrity services and thus can support the IC authentication protocols employed to counteract potential threats such as untrusted users accessing ICs. However, IC vendors raise concerns regarding the complexity of certain hash functions in terms of area overhead, the impact on the design flow, and testability. These concerns have motivated this work presenting a simple, yet effective, lightweight, scalable cryptographic hash function H2B. It builds on a hybrid ring generator, i.e., an area and time-optimized version of a linearfeedback shift register, which works in tandem with a nonlinear sequential circuitry whose feedback network comprises bent-like functions. A comprehensive evaluation, including test suits from the National Institute of Standards and Technology, shows the feasibility and efficiency of the proposed scheme and is reported herein.

Ring generators are high speed devices formed by transformations that alter the structure of conventional linear feedback shift registers (LFSRs) while preserving a transition function of the original circuits [8]. They feature a reduced number of levels of XOR logic, minimized internal fan-outs, and simplified layout and routing. This paper discusses hybrid ring generators – a new class of lightweight linear finite state machines. While they use the principal design rules of conventional ring generators, the new devices can reduce the number of XOR gates up to seven times compared to conventional rings implementing the same characteristic polynomial. It makes a substantial contribution toward the performance of linear circuits used in a variety of test applications. Several issues related to hybrid ring generators such as designing MISRs, programable PRPGs, or phase shifters are also discussed in the paper along with data providing architectural details of hybrid ring generators for sizes up to 256 bits.

Deterministic in-system tests begin to play an essential role in safety-critical applications, in large data centers, or in monitoring silicon aging, to name just a few. All of these ecosystems require periodic, high-quality tests to assure required test coverage and short test application, especially in designs that must test themselves during system operations. In order for deterministic tests to be in-system applicable, they should compact multimillion-bit test responses with unknown ($\rm X$) values to small signatures. This, in turn, allows for a much faster input-only streaming and a simultaneous reduction of the on-chip-stored test data volume, a system memory, and test time. Typically, the unknown states, whose sources vary from uninitialized memories to unpredictable last-minute timing violations, render signatures unusable. Hence, test response compaction requires some form of protection. This article presents a user-tunable X-masking scheme. It works synergistically with on-chip test compression logic by employing encoded test data to completely filter out unknown values that otherwise might reach a test response compactor, such as a multiple-input signature register or test result sticky bits used by the on-chip compare framework. It makes the proposed scheme a very versatile of its kind. Experimental results obtained for several industrial cores show feasibility and efficiency of the proposed scheme altogether with the actual impact of X-masking on various test-related statistics.

There are many schemes proposed to protect integrated circuits (ICs) against an unauthorized access and usage, or at least to mitigate security risks. They lay foundations for hardware roots of trust whose crucial security primitives are generators of truly random numbers. In particular, such generators are used to yield one-time challenges (nonces) supporting the IC authentication protocols employed to counteract potential threats such as untrusted users accessing ICs. However, IC vendors raise several concerns regarding the complexity of these solutions, both in terms of area overhead, the impact on the design flow, and testability. These concerns have motivated this work presenting a simple, yet effective, all-digital lightweight and self-testable random number generator to produce a nonce. It builds on a generic ring generator architecture, i.e., an area and time optimized version of a linear feedback shift register, driven by a multiple-output ring oscillator. A comprehensive evaluation, based on three statistical test suits from the National Institute of Standards and Technology and BSI, show feasibility and efficiency of the proposed scheme and are reported herein.

Test set compaction is one of the key steps of the postproduction test known to bring down test pattern counts. This, in turn, allows one to reduce the corresponding test data volume, test application time, and hence the cost of testing. This article presents a method that strives to reduce the number of automatic test pattern generation (ATPG)-produced deterministic test patterns to deliver compact test sets. In principle, the new scheme works with a meaningful representation of test patterns by using external and internal necessary assignments (NAs) to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the robust satisfiability (SAT)-based ATPG that produces a single test pattern for the entire group, thus making the resultant test set smaller in size. Experimental results obtained for 12 large industrial cores and stuck-at faults confirm superiority of the proposed scheme over the state-of-the-art test set compaction techniques and are reported herein.

In-system deterministic tests are used in safety-sensitive designs to assure high test coverage, short test time, and low data volume, typically through an input-streaming-only approach that allows a quick test delivery. The output side of the same scheme is, however, inherently vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to the last-minute timing violations. Typically, X values degrade test results and thus test response compaction requires some form of protection. This paper presents two X-masking schemes that complement the primary (or level-A) blocking of unknown values by filtering out those X states that escape the first stage of masking and shall not reach a test response compactor or test result sticky-bits deployed by the on-chip compare framework. Experimental results obtained for eleven industrial designs show feasibility and efficiency of the proposed schemes altogether with actual impact of X-masking on various test-related statistics.

In-field and in-system deterministic tests begin to play a pivotal role in safety-critical applications (compliant with regulations such as ISO 26262), in large data centers, or in monitoring silicon aging. All of them require periodic, high-quality tests to assure required test coverage and short test time in designs that must test themselves during system operations. In order for deterministic tests to be in-system applicable, they should compact multi-million-bit test responses with unknowns (X) to small signatures. This, in turn, allows for a much faster input-only streaming and reduction of the stored test data volume, a system memory, and test time. Typically, the unknown states, whose sources vary from uninitialized memories to unpredictable last-minute timing violations, render signatures unusable. Hence, test response compaction requires some form of protection. This paper presents a user-tunable X-masking scheme that employs compressed data to completely filter out unknown values that otherwise might reach a test response compactor such as a MISR or test result sticky-bits used by the on-chip compare framework. Experimental results obtained for several industrial cores show feasibility and efficiency of the proposed scheme altogether with actual impact of X-mask-in2 on various test-related statistics.

A hardware root of trust (RoT) is the foundation on which all secure operations of a circuit depend, including those related to DFT. Despite many countermeasures aimed at facing potential threats such as untrusted users accessing a test interface, IC vendors raise several concerns regarding the complexity of such solutions, both in terms of area overhead and the impact on the design flow. These concerns have motivated this work presenting a simple, yet effective, comprehensive and non-intrusive lightweight hardware root of trust to counteract scan-related security threats. It builds on and easily integrates with a Streaming Scan Network (SSN) technology and takes advantage of its inherent data scrambling and packetized test data distribution.

Contemporary and emergent automotive systems are heavily populated by complex integrated electronics. The number of safety-critical devices used in advanced driver-assistance systems or autonomous vehicles is growing with high-end models containing hundreds of embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that might be costly to engineer. Therefore, to address challenges posed by high-quality and long-term reliability requirements, this article presents low-cost test pattern generation schemes for a scan-based hybrid logic BIST of automotive ICs. It may allow one to optimize test coverage and test time during in-system test applications. The first presented technique deploys a seed-flipping PRPG to periodically complement PRPG stages in a methodical tree-traversal manner. The second scheme is based on a seed-sorting approach that allows additional tradeoffs between test data volume and test coverage. As shown in this article, the proposed schemes can be easily integrated with a test compression environment and deployed in different modes of in-system testing, such as key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.

Spin-transfer torque magnetoresistive random-access memories (STT-MRAMs) are gradually superseding conventional SRAMs as last-level cache in System-on-Chip designs. Their manufacturing process includes trimming a reference resistance in STT-MRAM modules to reliably determine the logic values of 0 and 1 during read operations. Typically, an on-chip trimming routine consists of multiple runs of a test algorithm with different settings of a trimming port. It may inherently produce a large number of mismatches. Diagnosis of such a sizeable volume of errors by means of existing memory built-in self-test (MBIST) schemes is either infeasible or a time-consuming and expensive process. In this paper, we propose a new memory fault diagnosis scheme capable of handling STT-MRAM-specific error rates in an efficient manner. It relies on a convolutional reduction of memory outputs and continuous shifting of the resultant data to a tester through a few output channels that are typically available in designs using an on-chip test compression technology, such as the embedded deterministic test. It is shown that processing the STT-MRAM output by using a convolutional compactor is a preferable solution for this type of applications, as it provides a high diagnostic resolution while incurring a low hardware overhead over traditional MBIST logic.

Test compaction and the associated test data compression are two key components of the post-production test as they reduce test pattern counts, the resultant test data volume, test application time, and hence the cost of testing. The paper describes a method that strives to reduce the number of ATPG-produced deterministic test patterns to deliver compact test sets. In principle, it is based on a dimensionality reduction paradigm by working with a meaningful representation of test patterns using external and internal necessary assignments to determine small groups of potentially compatible faults. These faults are subsequently retargeted by the robust SAT-based ATPG and its solvers producing a single test pattern for the entire group, thus making the resultant test set smaller in size. Experimental results obtained for several industrial designs and stuck-at faults confirm superiority of the proposed scheme over state-of-the-art test set compaction techniques and are reported herein.

Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradigms are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This article presents maXpress-an X-tolerant tunable compactor deploying a new scan chain selection mechanism capable of completely masking X states, as required by many in-system or one-directional streaming test applications, within redefinable groups of scan chains and designated scan shift cycles. The proposed scheme is also supporting separate observation scan chains that, in contrast to conventional scan, capture faulty effects every shift cycle, while their content is gradually shifted into a compactor shared with the remaining chains. In addition to a new layout-friendly architecture, the article proposes algorithms to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

As cars become increasingly computerized and their safety functions evolve rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is rising dramatically with high-end models containing hundreds of embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive systems. This article presents a scan-based test scheme optimizing test time and area overhead during manufacturing and in-system test of automotive electronics. The proposed scheme deploys observation test points that capture the faulty effects in every shift cycle into separate observation scan chains. To reduce area overhead, the scheme enables the sharing of flip-flops among control points. It is also shown how test points enhance test coverage (TC) in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine TC are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in test quality over traditional solutions.

As the use of electronic components grows rapidly in the automotive industry, the number of complex safety-critical devices used in advanced driver assistance systems or autonomous cars is rising with high-end models containing more than 200 embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that address challenges posed by high quality and long-term reliability requirements mandated, for example, by the ISO 26262 standard. The paper presents test pattern generation schemes for a scan-based logic BIST optimizing test coverage and test time during in-system test applications for automotive ICs. As a part of overall safety, they help in ensuring reliable operations of vehicle's electronics throughout their lifecycles. The proposed schemes can be deployed in different modes of in-system testing, including key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes.

There is a growing number of integrated circuits that deploy hybrid test schemes combining on-chip test compression with logic BIST, with both techniques working synergistically to deliver high quality tests. As their architectural differences are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized memory elements to unwrapped-for-test analog modules. Typically, X values degrade test results, and thus test response compaction schemes must be duly protected. This paper presents maXpress – an X-tolerant programmable compactor deploying a new scan chain selection mechanism capable of completely (as required by many in-system test applications) masking X states within redefinable groups of scan chains and designated scan shift cycles. In addition to the new architecture, the paper proposes an algorithm to automate maXpress control settings based on scan chain selection rules deployed to suppress X states. Experimental results obtained for a variety of industrial designs show feasibility and efficiency of the proposed scheme altogether with actual impact of X-masking on a resultant test coverage and test pattern counts.

This article presents a next-generation test data compression scheme. It builds on the isometric compression paradigm, but makes it more flexible and elevates encoding efficiency to values unachievable through state-of-the-art sequential compression schemes. Furthermore, its programmable selection of full-toggle scan chains ensures high test coverage and virtually eliminates compression aborts. The presented approach follows from a fundamental observation that among test cube care bits, only a very few have a status of necessary assignments (their locations cannot be changed), whereas the remaining ones have alternative sites. These test cubes are used to form circular test templates which synergistically control a decompressor and guide back ATPG to find assignments yielding highly compressible test patterns. A redesigned low-silicon-area decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. The experimental results obtained for large industrial designs and other benchmark circuits confirm the superiority of the proposed scheme over existing techniques and are reported herein.

As the automotive industry enters a period of rapid evolution changing the way cars are designed and produced, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing around 120 MCUs. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. This paper presents Stellar BIST-a next generation compression scheme for in-system automotive test. The proposed solution can work with any sequential test compression. It builds on a finding that certain clusters of test vectors are capable of detecting many random-resistant faults, where a cluster consists of a parent (base) pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant tradeoffs between storage requirements and test application time, critical for in-system automotive applications. The experimental results obtained for industrial designs and different fault models illustrate feasibility of the proposed test scheme and are reported herein.

As cars become increasingly computerized and their safety functions are evolving rapidly, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing more than a hundred embedded microcontrollers. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. The paper presents a scan-based LBIST scheme optimizing test time and area overhead during in-system test applications for automotive ICs. It ensures highly reliable operations of ICs for the duration of their lifespan. The proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. To reduce area overhead, the scheme takes advantage of a procedure allowing one to share flip-flops among control points. It is also shown how test points can enhance test coverage in the presence of cascaded clock gaters. Finally, processing challenges when fault simulating every scan shift cycle to determine observed faults are addressed. Experimental results obtained for contemporary automotive designs and reported herein show significant improvements in quality of test over traditional BIST schemes.

The semiconductor industry ramping up design capabilities for emerging technologies is facing unprecedented test quality and yield management challenges. To facilitate diagnosis of yield issues and to enable repair processes, an accurate defect isolation is needed with support of more advanced test, diagnostic, and yield analysis tools. Scan remains instrumental in developing more advanced DFT technologies, including logic BIST and on-chip test data compression. Its reliable operations are essential for test pattern bring-up, failure analysis, and yield learning. This paper demonstrates how to re-architect on-chip test data compression environment to enable multiple and repeated scan integrity tests for advanced test procedures, including various forms of stroboscopic electron-beam imaging and laser voltage imaging. The presented approach avoids the repetitive loading of scan chains and therefore reduces significantly test time and may support advanced diagnostic techniques. The new solution has virtually no area overhead, and does not compromise the performance of the original test logic.

Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs targeted for safety-critical systems. Test points, common in LBIST-ready designs, can help to reduce test time and the overall silicon overhead so that one can get desired test coverage with the minimal number of patterns. Typically, LBIST test points are dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG pattern counts (PCs) cannot guarantee desired random testability. In this paper, we present a hybrid test point technology designed to reduce deterministic PCs and to improve fault detection likelihood by means of the same minimal set of test points. The hybrid test points are subsequently deployed in a scan-based LBIST scheme addressing stringent test requirements of certain application domains such as the automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage. The new scheme is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid observation test points that capture faulty effects every shift cycle into dedicated scan chains. Their content is gradually shifted into a compactor shared with the remaining chains that deliver responses once a test pattern has been shifted-in. Experimental results obtained for industrial designs confirm feasibility of the new schemes, and they are reported herein.

The paper presents a novel test data compression scheme. This low-silicon-area solution builds on the isometric compression paradigm, but makes it more flexible, elevates encoding efficiency to values unachievable through any conventional type of sequential compression, and ensures high test coverage due to programmable selection of full toggle scan chains. The presented approach follows from a fundamental observation that only a few specified positions in test cubes are necessary to detect faults, while the remaining ones have alternative sites. Such test cubes are used to form circular test templates which synergistically control a decompressor and guide ATPG to find assignments yielding highly compressible test cubes. A redesigned decompressor is also capable of reducing switching rates in scan chains with a new test power control scheme. Experimental results obtained for large industrial designs confirm superiority of the proposed scheme over state-of-the-art techniques and are reported herein.

With the growing number of very complex safety-critical components used in advanced driver assistance systems and autonomous vehicles, integrated circuits in this area must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This, in turn, requires advanced test solutions that have to respond to challenges posed by automotive parts. This paper presents Stellar BIST - a deterministic two-level compression scheme for in-system automotive test. The proposed solution seamlessly integrates with any sequential test compression scheme and takes advantage of the fact that certain clusters of test vectors detect many random-resistant faults where a cluster consists of a parent pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant trade-offs between area and time, critical for in-system automotive applications. Experimental results obtained for large industrial designs with stuck-at and transition faults illustrate feasibility of the proposed test scheme and are reported herein.

This is the extended summary of the PhD thesis on new test point insertion techniques. The thesis provides a comprehensive study of innovative DFT schemes going far beyond traditional logic BIST-based applications of test points. The proposed methods visibly decrease pattern counts, reduce test generation and test application times, and increase test coverage by means of algorithms capable of identifying and resolving conflicts between circuit's internal signals. In particular, it is shown that new test points provide, on the average, 2×-3× increase in test compression for stuck-at, transition and cell-aware patterns. Furthermore, it is demonstrated that test-point-centric DFT logic can be successfully used to lock a circuit or hide its functionality. As a result, this approach improves the overall hardware security against reverse engineering, IC cloning, and IP theft.

This paper presents a new staggered test pattern generation scheme. It produces deterministic stimuli in the course of a test-per-clock-based process by using dedicated capture-per-cycle observation test points. These observation points, once inserted into a design, form dedicated scan chains with the capability of capturing test responses during shift cycles when other regular scan cells are loading test patterns. This new scan infrastructure enables one to generate more compact test patterns, reduce test pattern counts, systematically detect many additional faults, and keep the resultant silicon real-estate at the acceptable level. It appears that original scan cells of a design can provide good observability for staggered test patterns. Thus, capture-per-cycle observation test points are directly inserted at selected scan cells' inputs with a minimal impact on the design. Experimental results obtained for large industrial designs illustrate feasibility of the proposed ATPG and are reported herein.

Growing reverse-engineering attempts to steal or violate a design intellectual property (IP), or to identify the device technology in order to counterfeit integrated circuits (ICs), raise serious concerns in the IC design community. As the information derived from these practices can be used in a number of malicious ways, various active techniques have been proposed and deployed to protect IP, of which logic locking is a vital part. It allows inserting certain gates in a circuit's data path to lock outputs to fixed logic values, if a wrong unlocking key is applied. This paper demonstrates that test points-industry-proven design-for-test technology used primarily to enhance the overall design testability-can also be reused in the mission mode to lock the circuit, and thus to improve the hardware security against IP piracy. In particular, it is shown that test points can facilitate the hiding of design functionality from adversaries. As a result, not only is the overall design testability improved, but also effective protection against piracy through unauthorized excess production and other forms of IP theft is ensured. Experimental results on industrial designs with test points demonstrate that the proposed scheme is effective in achieving a desired degree of hardware obfuscation.

Several hard-to-detect faults occurring in read-only memories require complex test algorithms that make it difficult to perform accurate diagnosis in a reasonable time. The primary reason for this is a multitude of reference signatures that need to be stored and compared against the actual data obtained from a ROM-under-test in order to isolate the failing memory sites. This paper presents techniques that facilitate fault diagnosis when deploying complex test algorithms such as GALPAT or Walking 1/0. The new diagnostic techniques reduce processing time and a tester memory size such that it becomes feasible to identify hard-to-detect faults within a memory BIST infrastructure.

This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that addresses stringent test requirements of certain application domains such as the fast-growing automotive electronics market. These requirements, largely driven by safety standards, are met by significantly reducing test application time while preserving the high fault coverage of conventional BIST schemes. Alternatively, one may consider applying a much larger number of vectors within the same time interval. Although the new scheme may resemble traditional BIST logic, it is a combination of pseudorandom test patterns delivered in a test-per-clock fashion through conventional scan chains and per-cycle-driven hybrid test points that creates this new synergistic LBIST paradigm. The hybrid observation points, inserted at the most suitable locations, capture faulty effects every shift cycle into dedicated flip-flops that form separate scan chains. Their content is gradually shifted into a compactor, which is shared with the remaining scan chains that still deliver test responses captured once the entire test pattern has been shifted-in. Experimental results obtained for industrial designs illustrate feasibility of the proposed BIST scheme in terms of test time, test coverage, and area overhead, and they are reported herein.

This paper presents Star-EDT-a novel deterministic test compression scheme. The proposed solution seamlessly integrates with EDT-based compression and takes advantage of two key observations: 1) there exist clusters of test vectors that can detect many random-resistant faults with a cluster comprising a parent pattern and its derivatives obtained through simple transformations and 2) a significant majority of specified positions of ATPG-produced test cubes are typically clustered within a single or, at most, a few scan chains. The Star-EDT approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs, including those with a new class of test points aware of ATPG-induced conflicts, illustrate feasibility of the proposed deterministic test scheme and are reported herein. In particular, they confirm that the Star-EDT can act as a valuable form of deterministic BIST.

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of 2×-4× compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

This paper presents a novel scan-based design for test (DFT) paradigm. Compared with conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage or allows applying a much larger number of vectors within the same time interval. An equally important factor is the toggling activity during test-with this scheme, it remains similar to that of the mission mode. Several techniques are introduced that allow integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. The experimental results obtained for large and complex industrial application-specific IC designs illustrate the feasibility of the proposed test scheme despite additional costs and efforts entailed in consolidating architectural changes and operations across a DFT flow.

Recent reverse-engineering attempts to steal a competitive design intellectual property (IP) or to identify the device technology in order to counterfeit integrated circuits (ICs) have raised serious concerns in the IC design community. This paper demonstrates that test points - industry-proven design-for-test technology used to enhance the overall design testability - can also be deployed in the mission mode to obfuscate the circuit's structure, and thus to improve the hardware security against reverse engineering, IC cloning, and IP theft. In particular, it is shown how test points can facilitate the hiding of design functionality from adversaries. As a result, not only the overall design testability is improved, but also effective protection against reverse engineering and other forms of attacks is ensured.

Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during the test point selection process, and ATPG verification is run for every potential candidate. Experimental results show that functional flip-flops can be reused as drivers for more than 90% of the control points with the average of 5% penalty in pattern count increase as compared to methods using only dedicated flip-flops. After replacing dedicated flip-flops with functional flip-flops, conflict-aware test points can still achieve remarkable pattern count reductions.

Logic built-in self-test (LBIST), originally introduced for board, system, and in-field tests, is now being increasingly used with on-chip test compression. This hybrid approach allows LBIST to become a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs that are targeted for safety-critical and automotive systems. Test points are common in BIST-ready designs where they play a key role in reducing both test application time given a test coverage goal and the overall silicon overhead so that one can get a desired coverage with the minimal number of patterns. Unfortunately, these test points are typically dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG-based test pattern counts cannot guarantee desired random testability. Incompatibility of both types of test points has motivated research presented in this paper. We present a novel hybrid test point technology designed to both reduce deterministic pattern counts and improve fault detection likelihood by means of the same minimal set of test points. Experimental results obtained for large industrial designs illustrate feasibility of the proposed hybrid test points and are reported herein.

This paper presents a novel scan-based DFT paradigm. Compared to conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage, or allows applying much larger number of vectors within the same time interval. An equally important factor is the power dissipated during test - with the new scheme it remains similar to that of the mission mode. Several techniques are introduced that allow easy integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. Experimental results obtained for large and complex industrial ASIC designs illustrate feasibility of the proposed test schemes and are reported herein.

This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x -- 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

The introduction of FinFET technology has accelerated the adoption of patterns that target cell internal defects such as cell-aware tests. Even though cell-aware tests can replace stuck-at and transition patterns from the screening point of view, we have to address the increase in test data volume. This combined with the growing gate counts enabled by new technology nodes is driving the need for even greater compression levels. In this paper, we present a novel test points technology designed to reduce deterministic pattern counts for cell-aware tests. The technology is based on identification and resolution of conflicts across internal signals allowing ATPG to significantly increase the number of faults targeted by a single pattern. Experimental results on a number of industrial designs with test compression demonstrate that the proposed test points are effective in achieving, on average, a 3×–4× multiplicative increase in compression for 1-cycle and 2-cycle cell-aware patterns.

The paper presents a novel deterministic built-in self-test (BIST) scheme. The proposed solution seamlessly integrates with on-chip EDT-based decompression logic and takes advantage of two key observations: (1) specified positions of ATPG-produced test cubes are typically clustered within a single or a few scan chains for a small number of successive scan shift cycles, (2) only a small fraction of the specified positions are necessary to detect a fault, and most of the remaining ones have several alternatives that can be obtained by inverting preselected scan slices (all scan cells within a given cycle). The proposed approach elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed logic BIST scheme and are reported herein.

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents several techniques employed to resolve problems surfacing when applying scan bandwidth management to large industrial multicore system-on-chip (SoC) designs with embedded test data compression. These designs pose significant challenges to the channel management scheme, flow, and tools. This paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with embedded deterministic test-based test data compression. The same solutions allow efficient handling of physical constraints in realistic applications. Finally, state-of-the-art SoC test scheduling algorithms are rearchitected accordingly by making provisions for: 1) setting up time-effective test configurations; 2) optimization of SoC pin partitions; 3) allocation of core-level channels based on scan data volume; and 4) more flexible core-wise usage of automatic test equipment channel resources. A detailed case study is illustrated herein with a variety of experiments allowing one to learn how to tradeoff different architectures and test-related factors.

This paper describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Furthermore, this paper proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The proposed hybrid scheme efficiently combines test compression with LBIST, where both techniques can work synergistically to deliver high quality tests. Experimental results obtained for industrial designs illustrate the feasibility of the proposed test schemes and are reported herein.

This paper introduces a low-power test compression scheme that can also be used in a conventional BIST environment. The key contribution is an observation that simple broadcasting of a constant value to predetermined subsets of scan chains allows visible reductions of both toggling rates and pattern counts provided these subsets can be regrouped when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of the existing scan gating logic, its synergistic use with test compression algorithms yields a low scan load switching activity, reduced test time, and less intensive traffic of control data. Consequently, the proposed scheme helps to resolve problems related to test power dissipation and elevated test durations.

The paper presents a high-speed serial interface between external tester and Embedded Deterministic Test (EDT) compression logic hosted by SoC designs. With only a single bidirectional link, the system is capable of feeding distributed heterogeneous cores with hundreds of test channels. Moreover, it synergistically supports EDT bandwidth management to improve the overall test performance. A detailed study indicates a high potential of the serial EDT approach to handle large multicore SoC designs by deploying only a single serial interface and completing the entire test for stuck-at faults in less than one second. Experiments conducted with the help of FPGA -- based evaluation platform confirm feasibility and a high effectiveness of the proposed solution.

On-chip test compression has quickly established itself as one of the mainstream design-for-test (DFT) methodologies. It assumes that a tester delivers test patterns in a compressed form, and on-chip decompressors expand them into actual data loaded into scan chains. This paper presents a new and comprehensive method to boost performance of sequential test compression and ATPG operations. The approach is primarily aimed at reducing CPU time associated with generating and compressing test patterns. It prevents ATPG from assigning specified values to many inputs in order to cut down a time-consuming backtracking process needed to resolve conflicts leading to compression aborts. The proposed scheme efficiently combines test compression constraints with ATPG. Experimental results obtained for industrial designs illustrate feasibility of the proposed scheme and are reported herein.

In the paper, two methods of ensuring high quality of the memory built-in self-test tools are presented. The described ideas illustrate general methods and are applicable to any commercial memory BIST tool. The first solution describes controller emulation in order to validate each step of the real controller's operations. The second approach presents a way to determine the test algorithms' fault coverage by means of the memory fault simulator. The experimental results show functional benefits and effectiveness of the proposed solutions.

The paper presents a novel test data compression scheme. The invention follows from a fundamental observation that in a typical test cube only a small portion of the specified positions are necessary to detect a fault, and most of the remaining ones have many alternatives. The necessary assignments are used to form test templates which both control a decompressor to guarantee the necessary assignments and guide ATPG to find alternative assignments to produce highly compressible test cubes. The proposed approach synergistically elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. It also reduces, in a user-controlled manner, switching rates in scan chains with minimal hardware modification. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Due to a production error, an incorrect figure was used for Fig. 8 on p. 1781 in the above paper (ibid., vol. 32, no. 11, pp. 1776-1786, Nov. 2013). The correct figure is presented here.

This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

Through-silicon vias (TSVs) are crucial elements of 3-D bonded integrated circuits. Since they connect different layers of 3-D stacks, their proper operation is an essential prerequisite for the system function. This paper describes a procedure for deriving fault diagnosis test sequences to identify single and multiple defective TSVs. Additional experimental results obtained for pseudorandom patterns illustrate feasibility and robustness of the proposed test schemes in terms of their detection and diagnostic capabilities and are reported herein.

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to test bandwidth management is demonstrated by running experiments on several industrial SoC designs and is reported herein.

The paper presents an extended summary of the PhD thesis that tackles a low power decompression of test cubes in EDT environment and compaction of test responses in the presence of unknown states. The proposed low power decompression schemes allow one to reduce the load and unload switching activity by more than 93% and capture transitions by 52%. The X-masking scheme introduced in the thesis offers up to 48,000 x compression of control data, and eliminates all unknown states from test responses.

This paper describes a low power programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared to best-to-date BIST-based PRPGs. We introduce a method to automatically select several controls of the generator allowing easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

This paper presents a new pseudorandom test pattern generator with preselected toggling (PRESTO) activity. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter and armed with a number of features that allows this device to produce binary sequences with low toggling (switching) rates while preserving test coverage achievable by the best-to-date conventional BIST-based PRPGs with negligible impact on test application time.

This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface with automatic test equipment through an optimized number of channels. They are well suited for SoC devices comprising both nonisolated cores, i.e., blocks that occasionally need to be tested simultaneously, and completely wrapped modules. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application schemes and are reported herein.

This paper discusses a low-power test scheme compatible with both test compression and built-in self-test environments. The key contribution is a detailed analysis showing that a simple power-aware controller may allow significant reductions of toggling rates when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of existing DFT logic, its use results in a low switching activity during all phases of scan test: loading, capture, and unloading. It reduces power consumption to or below a level of a functional mode, thus helping to resolve problems related to power dissipation, voltage drop, and increased temperature.

In this paper we examine several embedded low power test schemes that we have proposed over the last few years. These solutions are aimed at reducing the switching activity during all scan-based test operations, particularly including those developed for BIST or deployed to perform on-chip test data compression.

This paper presents a new BIST-based fault diagnosis scheme for non-march tests of complexity O(n^2). It can be used to identify failures in embedded memory arrays using galloping pattern tests. The proposed solution employs scalable and flexible logic to record test responses, with no negative impact on at-speed test. It enables recording of responses produced by failures hard to handle by conventional march tests. This, in turn, allows accurate isolation of memory failures during off-line processing.

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal- spatial and time- signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.

This paper presents a study addressing the challenge of interfacing automatic test equipment (ATE) with on-chip decompression logic deployed by system-on-chip designs or modular decompression environments. The ability of the proposed scheme to improve the encoding bandwidth by reusing groups of scan chains for test data storage has been measured on industrial designs and is reported herein.

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal—spatial and time—signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.

The embedded deterministic test-based compression uses cube merging to reduce a pattern count, the amount of test data, and test time. It gradually expands a test pattern by incorporating compatible test cubes. This paper demonstrates that compression ratios can be order of magnitude higher, if the cube merging continues despite conflicts on certain positions. Our novel solution produces test clusters, each comprising a parent pattern and a number of its derivatives obtained by imposing extra bits on it. In order to load scan chains with patterns that feature original test cubes, only data necessary to recreate parent patterns as well as information regarding locations and values of the corresponding conflicting bits are required. A test controller can then deliver tests by repeatedly applying the same parent pattern, every time using a different control pattern to decide whether a given scan chain receives data from the parent pattern, or another pattern is used instead to recover content of the original test cube. Compression of incompatible test cubes preserves all benefits of continuous flow decompression and offers compression ratios of order 1000× with encoding efficiency much higher than 1.0. We also demonstrate that test clusters make it possible to deliver test patterns in a flexible power-aware fashion. This framework achieves significant reductions in switching activity during scan loading as well as additional test data volume reductions due to encoding algorithms employed to compress parent and control vectors.

This paper presents a built-in self-test (BIST)-based scheme for fault diagnosis that can be used to identify permanent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

This paper presents a novel scheme to address the challenge of identifying failing scan cells from production test responses in the presence of scan compression. The scheme is based on a very simple test response compactor employing orthogonal - spatial and time - signatures. The advantage of this scheme as compared to previous work in this field is the simple and incremental nature of the compaction hardware required. The ability of the scheme to accurately identify failing scan cells from compacted responses has been measured on production fail data from five industrial designs and is reported herein.

The paper presents a new power-aware test scheme compatible with a newly proposed test compression environment based on deterministic clustering of test cubes with conflicts. The key contribution is a flexible test application framework that achieves significant reductions in switching activity during scan loading by means of a tri-modal test data decompressor.

The paper presents a preemptive test application scheme for system-on-chip (SoC) designs with EDT-based compression. It seamlessly combines a new test data reduction technique with a test scheduling algorithm and a novel test access mechanism. It is particularly well suited for SoC devices comprising non-isolated cores, i.e., blocks that occasionally need to be tested simultaneously.

Unknown (X) states are increasingly often identified as having potential for rendering semiconductor tests useless. One of the key requirements for a reliable test response compactor is, therefore, to preserve observability of any scan cell for a wide range of X-profiles while maintaining very high-compaction ratios, providing ability to detect a variety of failures found in real silicon, and assuring design simplicity. We have proposed a fully X-tolerant test response compaction scheme which is based on a flexible scan chain selection mechanism. This new approach delivers extremely high compression of test results by observing that X states are typically not randomly distributed in test responses. Identical or similar patterns of correlated X states let the proposed scheme reduce the size of a scan chain selector and the amount of test data used to control it. It handles, moreover, a wide range of unknown state profiles such that all X states, including those being clustered and of high density, are suppressed in a per-cycle mode without compromising the test quality.

Embedded memories are increasingly identified as having potential for introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in fault diagnosis techniques. In particular, time-related or complex read faults that originate in the highest density areas of semiconductor designs require new methods to diagnose more complex faults affecting large groups of memory cells. This paper presents a built-in self-test (BIST)-based fault diagnosis scheme that can be used to identify a variety of failures in embedded random-access memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way test responses are processed allows accurate and time-efficient reconstruction of error bitmaps. The proposed diagnostic algorithms use a number of techniques, including discrete logarithm-based counting with ring generators acting as very fast event counters and signature analyzers. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency.

The presented compression scheme is a novel solution that is based on deterministic vector clustering and encompasses three data reduction features in one on-chip decoding system. The approach preserves all benefits of continuous flow decompression and offers compression ratios of order 1000x with encoding efficiency much higher than 1.00.

The paper presents a BIST-based scheme for fault diagnosis that can be used to identify permanent and address independent failures in embedded read-only memories. The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of time-related faults.

The paper presents a new scan chain selection scheme for response compaction. The proposed solution performs selective masking of scan chains and handles a wide range of unknown state profiles, such that all X states can be eliminated in a per-cycle mode while preserving high observability of scan cells that capture errors.

This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip continuous-flow decompressor. Its synergistic use with a power-aware scan controller allows a significant reduction of toggling rates when feeding scan chains with decompressed test patterns. While the proposed solution requires minimal modifications of the existing design for test logic, experiments indicate that its use results in a low switching activity which reduces power consumption to or below a level of a functional mode. It resolves problems related to power dissipation, voltage drop, and increased temperature. Our approach integrates seamlessly with test logic synthesis flow, and it does not compromise compression ratios. It fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.

This paper presents a new and comprehensive power-aware test scheme compatible with a test compression environment. The key contribution of the paper is a flexible test application framework that achieves significant reductions in switching activity during all phases of scan test: scan loading, unloading, and capture.

The paper presents a BIST-based fault diagnosis scheme that can be used to identify a variety of failures in embedded memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way the test responses are processed allows accurate reconstruction of error bitmaps.

This paper presents a new low-power test scheme integrated with the embedded deterministic test environment. The key contribution of this paper is a flexible test cube encoding scheme, which, in conjunction with a continuous flow decompressor, allows one to significantly reduce toggling rates when test patterns are fed into scan chains. The proposed solution requires neither additional design for testability logic nor modifications to the circuit under test. Experimental results obtained for industrial designs indicate that using this nonintrusive technique reduces switching activity to such extent that the resultant scan-in power consumption is similar to that of the functional mode, thus alleviating problems that are related to average and peak power dissipation, overheating, and risk of reliability degradation. Our approach seamlessly integrates with test logic synthesis flow, and it does not compromise compression ratios. Moreover, it fits well into various design paradigms, including modular design flow where modules come with individual decompressors and compactors.

This paper presents X-Press - a new two-stage test-response compactor that can be easily integrated with a multiple scan-chain environment. This compactor preserves all benefits of spatial compaction and offers, due to its overdrive sequential section, compression much higher than the ratio of scan chains to compactor outputs. X-Press is also capable of handling a wide range of unknown (X) state profiles by deploying a two-level scan-chain-selection mechanism. In addition to a new compactor architecture, original contributions of this paper include a detailed analysis of two-level error masking caused by X states and a new algorithm to both rank scan chains and then to determine, in per-pattern mode, scan-chain-selection rules used to suppress X states. Experimental results obtained for a variety of designs show feasibility and efficiency of the proposed compaction scheme, altogether with actual impact of X states on a test-pattern count. Finally, diagnostic capabilities of the proposed scheme accompanied by further experimental results are also analyzed.

The paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces significantly switching rates in scan chains with minimal hardware modification. Experimental results obtained for industrial circuits clearly indicate that switching activity can be reduced up to 150 times along with improved compression ratios.

This paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces switching rates in scan chains with no hardware modification. Experimental results obtained for industrial circuits indicate that switching activity can be reduced up to 23 times.

This paper presents new nonadaptive fault-diagnosis techniques for scan-based designs. They guarantee accurate and time-efficient identification of failing scan cells based on results of convolutional compaction of test responses. The essence of the method is to use a branch-and-bound algorithm to narrow the set of scan cells down to certain sites that are most likely to capture faulty signals. This search is guided by a number of heuristics and self-learned information used to accelerate the diagnosis process for the subsequent test patterns. A variety of experimental results for benchmark circuits, industrial designs, and real fail logs confirm the feasibility of the proposed approach even in the presence of unknown states. The scheme remains consistent with a single test session scenario and allows high-volume in-production diagnosis.

The paper presents an efficient method for synthesis of scan chain selection logic. It is capable of acting as a flexible X-control logic for test response compactors. The same circuitry can also be employed to selectively gate scan chains for diagnostic purposes.

This paper introduces a new test response compaction scheme that rests on convolutional compactors. The resultant compression, however, is not limited by the ratio of scan chains to compactor outputs. This enhanced convolutional compactor, similarly to its origin, is capable of handling unknown states and detecting multiple errors. The experimental results demonstrate efficiency of the proposed scheme

The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution

This paper presents an enhanced architecture of on-chip pseudorandom test pattern generators, test data decompressors, and test response compactors based on ring generators. The new structure is aimed at improving layout and routing properties while, at the same time, reducing propagation delays introduced by associated phase shifters.

This paper describes a fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss Jordan elimination method.

The paper presents non-adaptive fault diagnosis techniques for scan-based designs. These schemes guarantee accurate and time-efficient identification of failing scan cells based on results of a convolutional test response compaction in the presence of unknown states

The paper presents a very efficient method for synthesis of convolutional compactors capable of tolerating a number of unknown states in a single time frame while providing very high compaction ratios.

This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100/spl times/, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits.

The paper introduces a new non-adaptive fault diagnosis technique for scan-based designs. The proposed scheme guarantees accurate and time-efficient identification of failing scan cells based on results of a convolutional test response compaction.

The paper presents enhanced architectures of pseudo-random test pattern generators and on-chip test data decompressors based on ring generators. The new structures are aimed at improving their layout and routing properties while at the same time reducing propagation delays introduced by associated phase shifters.

This paper presents a novel methodology of designing generators and compactors of test data. The essence of the proposed approach is to use a set of transformations, which alters the structure of the conventional linear feedback shift registers (LFSRs) while preserving the transition function of the original circuits. It is shown that after applying the transition function preserving transformations in a certain order, the resultant circuits feature a significantly reduced the number of levels of XOR logic, minimized internal fanouts, and simplified circuit layout and routing, as compared to previous schemes based on external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial. Consequently, the proposed devices can operate at higher speeds than those of conventional solutions and become highly modular structures.

This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG methodology and adopts a very simple flow. It is nonintrusive as it does not require any modifications to the core logic such as the insertion of test points or logic bounding unknown states. The EDT scheme consists of logic embedded on a chip and a new deterministic test-pattern generation technique. The main contributions of the paper are test-stimuli compression schemes that allow us to deliver test data to the on-chip continuous-flow decompressor. In particular, it can be done by repeating certain patterns at the rates, which are adjusted to the requirements of the test cubes. Experimental results show that for industrial circuits with test cubes with very low fill rates, ranging from 3% to 0.2%, these schemes result in compression ratios of 30 to 500 times. A comprehensive analysis of the encoding efficiency of the proposed compression schemes is also provided.

We examine various forms of embedded deterministic test with particular emphasis on input stimuli compression and test response compaction schemes. Subsequently, the embedded deterministic test (EOT) scheme, which significantly reduces manufacturing test cost by providing a dramatic reduction in scan test data volume and scan test time, is discussed.

This paper introduces a finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. A convolutional compactor can be easily configured into a MISR that preserves most of these properties. Experimental results demonstrate the efficiency of compaction for several industrial circuits.

This paper presents a new highly modular architecture of generators and compactors of test patterns. This structure has fewer levels of logic, smaller fan-out, reduced area, and operates at faster speed than external feedback LFSRs, internal feedback LFSRs, and cellular automata, all implementing the same characteristic polynomial.

This paper introduces embedded deterministic test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.

This paper presents a new pseudoexhaustive test methodology for digital finite impulse response (FIR) filters. The proposed scheme can be employed to detect any combinational faults within the basic cell of the functional units occurring in linear phase comb filters, trees of sign-extended adders and phase-shift multipliers. It uses additive generators as a source of pseudoexhaustive patterns to systematically test all FIR filter building blocks.

The probability of obtaining desired test patterns in subsequences generated by two-dimensional test pattern generators is examined. Various architectures of generators comprising of linear feedback shift registers, cellular automata and associated phase shifters are thoroughly investigated. Two new algorithms that can be employed to synthesize phase shifters minimizing linear dependencies and assuring highly balanced usage of all generator stages are also introduced.

The paper presents a novel, comprehensive and systematic methodology, which can be used to automate synthesis of cellular automata-based test pattern generators with phase shifters. First, a very fast and simple simulation framework is proposed to either verify or generate maximum-length linear finite state machines such as cellular automata or linear feedback shift registers. Subsequently, a new framework is presented for efficient selection of phase shifters that satisfy criteria of channel separation and circuit complexity. As shown in the paper, it is possible to synthesize, in a time-efficient manner, very large cellular automata and their corresponding fast phase shifters for built-in self-test applications with guaranteed structural and functional properties.

This paper presents novel systematic design techniques for the automated register transfer level synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by pseudorandom test pattern generators driving parallel scan chains. Using a concept of linear feedback shift register (LFSR) duality this paper relates the logical states of LFSRs and circuits spacing their inputs to each of the output channels. Consequently, the method generates a phase-shifter network satisfying criteria of channel separation and circuit complexity by taking advantage of simple logic simulation of the LFSRs. It is shown that it is possible to synthesize in a time-efficient manner very large and fast phase shifters for built-in self-test applications with guaranteed minimum phaseshifts between scan chains, and very low delay and area of virtually one two-way XOR gate/channel.

The paper presents novel algorithms for the automated synthesis of cellular automata-based test generators with phase shifters. As shown in the paper, it is possible to synthesize in time-efficient manner very large cellular automata and their corresponding fast phase shifters for BIST applications with guaranteed structural and functional properties.

The paper presents a comparative study of randomness properties of patterns generated by one-dimensional linear hybrid cellular automata (LHCA) and linear feedback shift registers (LFSRs) with phase shifters on their outputs. It is shown that properly synthesized phase shifters allow LFSRs to match performance of the LHCAs as pseudo-random pattern generators (PRPGs), in marked contrast to several suggestions that LHCAs can outperform LFSRs in variety of testing applications.

The paper presents a new fault diagnosis technique for scan-based designs with BIST. It can be used for nonadaptive identification of the scan cells that are driven by erroneous signals. The proposed scheme employs a pseudorandom scan cell selection routine which, in conjunction with a conventional signature analysis and simple reasoning procedure, allows flexible trade-offs between the test application time and the diagnostic resolution.

The paper presents a new modular logic BIST architecture for intellectual property (IF) cores and block-oriented design methodology. The scheme involves two-step development process: design and analysis of BIST-ready IP cores and system integration. A BIST-ready core has inserted scan chains, test points, a repeater with phase shifter to perform serial to parallel conversion of test vectors, and a space-time test-response compactor. It is also simulated to determine its fault coverage and signature for a specified configuration of BIST hardware. Particulars of a method to compute the composite signature for the whole design based on signatures representing individual cores are presented altogether with a new technique to expand test vectors. At the system ASIC level, the paper demonstrates how multiple cores can be seamlessly integrated and then tested in exactly the same manner as they were analyzed by sharing the same BIST controller.

The paper introduces a new algorithm for the automated synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by two-dimensional test generators. The algorithms presented in the paper synthesize in a time-efficient manner very large and fast phase shifters for built in self-test environment, with guaranteed minimal phase shifts between scan chains, and very low delay and area of virtually one 2-way XOR gate per channel.

The paper presents novel systematic design techniques for the automated synthesis of phase shifter circuits used to remove effects of structural dependencies featured by test generators driving parallel scan chains. As shown in the paper, it is possible to synthesize very large and fast phase shifters for BIST applications with guaranteed phaseshifts between scan chains and very small number of gates per channel.

The paper presents an efficient scheme to compress and decompress in parallel deterministic test patterns for circuits with multiple scan chains. It employs a boundary-scan-based environment for high quality testing with flexible trade-offs between test data volume and test application time while achieving a complete fault coverage for any fault model for which test cubes are obtainable. It also reduces bandwidth requirements, as all test cube transfers involve compressed data. The test patterns are generated by the reseeding of a two-dimensional hardware structure which is comprised of a linear feedback shift register (LFSR), a network of exclusive-or (XOR) gates used to scramble the bits of test vectors, and extra feedbacks which allow including internal scan flip-flops into the decompressor structure to minimize the area overhead. The test data decompressor operates in two modes: pseudorandom and deterministic. In the first mode, the pseudorandom pattern generator (PRPG) is used purely as a generator of test vectors. In the latter case, variable-length seeds are serially scanned through the boundary-scan interface into the PRPG and parts of internal scan chains and, subsequently, a decompression is performed in parallel by means of the PRPG and selected scan flip-flops interconnected to form the decompression device. Extensive experiments with the largest ISCAS' 89 benchmarks show that the proposed technique greatly reduces the amount of test data in a cost effective manner.

This paper presents a new pseudo-exhaustive test methodology for digital finite impulse response (FIR) filters. The proposed scheme can be employed in a built-in self-test (BIST) environment to detect any combinational faults occurring in linear phase comb filters, trees of sign-extended adders and phase-shift multipliers. It uses additive generators as a source of pseudo-exhaustive patterns to test systematically all FIR filter building blocks.

The paper presents a new fault diagnosis technique for scan-based BIST designs. It can be used for non-adaptive identification of the scan cells that are driven by erroneous signals, irrespective of the error multiplicity. The proposed scheme employs a simple scan cell selection hardware which in conjunction with a conventional signature analysis allows flexible tradeoffs between the test application time and the diagnostic resolution.

The usage of multipliers in fixed-width data-dominated architectures (also termed data paths) poses serious testability problems. Due to truncation of their outputs, the fault observability of the multipliers degrades, and the resulting output patterns are inadequate to completely test functional blocks that are driven by them. Consequently, the overall random pattern testability of data paths deteriorates substantially. In this paper, we propose new generic design schemes, based on residue number system arithmetic, to improve the overall testability of data paths. The approach uses, in the test mode, the truncated least significant bits of the product to increase the variety of patterns at the output of a multiplier. This, in turn, improves the fault detectability of multipliers, and consequently, have a remarkable impact on the overall testability of data paths. The proposed techniques can be incorporated with a minimal performance degradation and area overhead, and are independent of the multiplier architecture. Experimental analysis performed on four high-level synthesis benchmarks exhibits a significant improvement in the overall testability of the corresponding data-path implementations.

A new built-in self-test (BIST) methodology is presented in which all generation and compaction functions are executed by basic building blocks such as adders, ALU's, and multipliers, performing regular arithmetic functions in digital signal processing (DSP) cores. It is demonstrated how these components are themselves tested, and subsequently used to perform more complex testing functions. The need for extra hardware is either entirely eliminated or drastically reduced, test vectors can be easily distributed to different modules of the system, test responses can be collected in parallel, and there is virtually no performance degradation. As an integral part of the proposed BIST environment, arithmetic two-dimensional (2-D) generators of pseudorandom test vectors are also introduced to further integrate the scheme with parallel scan and boundary scan designs used to test peripheral devices of the core.

This paper presents a new effective scheme to decompress in parallel deterministic test patterns for circuits with multiple scan chains. Two implementations of the scheme are discussed. In the first one, the patterns are generated by the reseeding of a hardware structure which is mostly comprised of the already existing DFT environment. In the second approach, the patterns are generated through the execution of a program on a simple embedded processor. Extensive experiments with the largest ISCAS'89 benchmarks show that the proposed technique greatly reduces the amount of test data with low cost. Efficient automatic test pattern generation algorithms are also presented to enhance the efficiency of the proposed approach.

The paper describes various techniques to increase the speed of time-division switches to support rates of 600 Mb/s and beyond. The issue of multirate switching, essential to BISDN applications, is also addressed. Architectures of RAM- and shift-register-based time switches are discussed and compared. Some representative structures of time-division switch fabrics applicable to BISDN are presented.

Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose processors. The resultant test patterns, generated by continuously accumulating a constant value, provide a complete state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme (Rajski and Tyszer, 1993) facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and no area overhead.

The probability of linear dependency in subsequences generated by linear feedback shift registers is examined. It is shown that this probability for a short subsequence, e.g., a sequence defined by the length of a scan chain, can be much higher than that for an entire m-sequence.

This paper demonstrates how fault simulation of building blocks found in data-path architectures can be performed extremely efficiently and accurately by taking advantage of their simple functional models and structural regularity.This technique can be used to accelerate the simulation of those blocks in virtually any fault simulation environment, resulting in fault simulation algorithms that can perform fault grading in a very demanding BIST environment.

The usage of multipliers in the increasingly demanding fixed-width data path architectures poses serious testability problems. Their truncated outputs not only degrade the fault observability, but the output responses of multipliers are inadequate to completely test functional blocks that are driven by them. In this paper, we propose a new design for testability scheme to improve the overall testability of data paths. The methodology takes into account the truncated least significant bits of the product in the test mode to increase the variety of patterns at the output of a multiplier. The proposed techniques are part of the Arithmetic Built-in Self Test methodology and can be incorporated with a minimal performance degradation and area overhead.

A novel highly efficient fault simulation technique targeted for circuits produced through high-level synthesis is presented. The technique combines hierarchical and functional fault simulation of commonly used building blocks that have regular structures. Comparison with gate-level simulation demonstrates the advantage of using this technique for this class of circuits.

In this paper, we propose an entirely new Built-in Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to generate test vectors and compact test responses. The paper employs state coverage to evaluate testability in an abstract level, and subsequently, use it to guide the synthesis of testable circuits.

This paper presents a new and efficient scheme to decompress a set of deterministic test vectors for circuits with scan. The scheme is based on the reseeding of a Multiple Polynomial Linear Feedback Shift Register (MP-LFSR) but uses variable-length seeds to improve the encoding efficiency of test vectors with a wide variation in their number of specified bits. The paper analyzes the effectiveness of this novel approach both theoretically and through extensive experiments. A modular design of the decompression hardware re-uses the same LFSR used for pseudo-random vector generation and scan registers to minimize the area overhead.

An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is introduced. The asymptotic and transient coverage drop introduced by accumulators with binary and 1's complement adders is studied using Markov chain models. It is proven that the asymptotic coverage drop in ABC with binary adders is 2/sup -k/, where k is the number of bits in the adder that the fault can reach. In ABC with 1's complement adders, the asymptotic coverage drop for a fairly general class of faults is (2n-1)/sup -1/, where n is the total number of bits. The analysis of transient behavior relates the coverage drop with the probability of fault injection, the size of the accumulator, and the length of the test experiment. The process is characterized by damping factors derived for various values of these parameters.>

A recursive technique for generating exhaustive patterns is presented. The method is optimal, i.e., in one experiment it covers exhaustively every block of k adjacent inputs in the first 2/sup k/ vectors. Implementation methods based on characteristic functions of test vectors are provided. They include a parallel pattern generator employing an exclusive-or array, and two serial generators that can be easily adopted in a scan-based built-in self-test environment.>

An accumulator-based compaction (ABC) scheme for parallel compaction of test responses is presented. In this scheme an accumulator with an n-bit binary adder is slightly modified such that the quality of compaction defined by the asymptotic coverage drop is similar to that offered by shift registers with irreducible polynomials of cellular automata. A Markov-chain model is used to analyze both the asymptotic coverage drop introduced by this scheme, and its transient behavior. It is shown that the asymptotic coverage drop depends both on the size of the accumulator and the probability of a fault injection. The upper bound of the coverage drop during the transition phrase is also provided. The proposed scheme is compatible with the width of the data path, and the test can be applied at the normal mode speed. The minimal hardware overhead involves only one-bit register to implement the feedback between the carry-out and carry-in lines.>

A coupling fault diagnosis procedure is proposed for digital switching networks constructed of uniform time-division switches. The procedure is executed in two phases. Each phase consists of eight test steps; the number of tests for detecting the most likely coupling faults inside a single switch is independent of the network size. The concept of primitive and convolutional test vectors is introduced in order to analyze test stimuli applied to successive switches during the test. The approach can be easily adapted for use in many modern digital exchanges.>

The authors study the relation between the length of the linear feedback shift register (LFSR), the size of the circuit (which defines the size of the fault list), and the quality of diagnostic resolution. They present an analytical model that is used to obtain a simple formula determining the fraction of faults that are uniquely diagnosed for a given circuit size and the LFSR length. The model is verified through extensive experiments on benchmark circuits.>

The problem of pattern-sensitive fault detection in integrated time-division switches is discussed. It is shown that high fault coverage can be obtained by applying random test vectors produced by a maximum-length linear feedback shift register. Two tester architecture solutions are proposed.>

An examination was made of the diagnostic properties of signature analysis. By theoretical and experimental studies the authors derived the probabilities that a given number of signatures occur during a test, and that a given number of signatures will be produced uniquely (i.e. by one fault). These characteristics were validated by a series of simulations of the benchmark circuits under test together with a response compaction procedure using linear feedback shift registers (LFSRs) implementing primitive polynomials. The experimental results confirm the validity of the theoretical model. The authors perform further calculations in order to reveal some important relationships between the size of the used LFSR, the total number of faults and the diagnostic resolution of signature analysis. Indeed, these results provide justification for the adoption of a simple formula that encompasses all the factors considered in the signature analysis compaction technique. Because of its simplicity it can be used directly in VLSI BIST design as well as in a wide range of other applications.>

A detection scheme for coupling faults for integrated digital time-division switches is proposed. It is shown that a low overhead is necessary to improve fault detectability. Based on the proposed augmentation of a standard time switch, a new test procedure that possesses the following properties is developed: it guarantees a detection of all possible coupling faults in both data and control memory, and the number of tests is minimal. >

Methods of fault detection and location for separate digital switching matrices as well as a wide class of switching networks are proposed. First, it is assumed that stuck-type faults can affect only a single component of a network. A model of a switching matrix is presented and fault equivalences are shown. After the discussion of single-switch diagnosis, test vectors and connection settings for identification of a single faulty switch in multistage networks are proposed. To avoid the masking effects, the notions of an H-test vector and an H-assignment are introduced. In the proposed approach, tests for space and time switching are performed separately. The problem of multiple fault detection is also considered.>

Certain fault-tolerant multiprocessor networks that can emulate linear array interconnections are considered. The system is fault tolerant of (m-1) node and link failures. One of the particularly attractive features of this network is that it allows for a linear array structure starting with any node even in spite of (m-2) faults. The configuration algorithm is fully distributed, and is performed on the basis of test results obtained from nonfaulty processors only. A simple fault identification procedure is developed using the above routing algorithm.>

It is relatively easy to generate a complete single contact fault detection test set Tc for a PLA. However such a test set may fail to detect all multiple faults due to the phenomenon of masking. In previous papers attempting to quantitatively predict the multiple fault coverage capability of a single fault detection test set Tc in PLA's, it was proved that every multiple contact fault in an irredundant PLA is detected by Tc if the multiple fault does not contain any four-way masking cycle. In this correspondence, the masking relations are studied in detail and it is shown that Tc in fact detects a signifilcant percentage of faults with four-way masking. Based on these results more realistic bounds of the coverage capability of Tc are determined. It is shown that the multiple fault coverage ratio of Tc increases with the increasing number m of rows of a PLA and for m = 24 Tc detects 99 percent of all contact faults of size 8 or less.

The increasing number of applications of programmable logic arrays (PLA's) has evoked the development of test generation methods for these circuits. There are known methods for complete single contact fault detection test set generation. These test sets fail to detect all multiple faults in a PLA due to the phenomenon of masking. In this correspondence, we present a method to quantitively predict the multiple fault coverage capability of a single fault detection test set in a PLA. The method enables us to determine the coverage ratio, which is defined as the ratio of the number of multiple contact faults detected by a single fault test Tcto the total number of all multiple faults. It is shown that the multiple fault coverage ratio of Tcdrops with an increasing size of faults, and most unexpectedly, the ratio increases with an increasing number of rows. The number of crosspoints in one product line has very little influence on the ratio.