The authors present a scan-based testability system that is an integral part of the cell-based design system at Microelectronics Center of North Carolina. The basic system consists of five modules: a scan-based audit to verify compliance with scan-based rules, a testability assessment module that projects fault coverage before any patterns are applied, a fast fault simulator that grades random and user-supplied patterns, an algorithmic test-pattern generator that produces test for faults that resist detection with random patterns or declares them redundant, and a test-pattern compactor to further reduce the size of the test-pattern set. The system serves as a platform for research into hierarchical methods, redundancy identification and removal, automated test point insertion, improved random test pattern generation, fault simulation, and boundary scan.>

The authors present a method for transforming multilevel equations into a gate-level netlist of a given technology. The proposed mapping procedure performs multiple mappings, each with randomly selected program parameters. The number of mappings is user-settable, and it offers the designer an option to trade off CPU runtime for better results. This feature is important to designers who begin by exploring the space of architectural possibilities, then finally create a specific, highly optimized circuit. The proposed technology mapping method has been implemented in C as a logic-design tool (McMAP) that takes full advantage of any gate library's timing and area information. Using default parameter settings, the tool synthesized several standard benchmark examples yielding higher-quality circuits with lower CPU requirements than previously reported.>

This paper presents ESPRIT, an automatic test pattern generation (ATPG) system for testing single stuck-at faults in combinational logic. ESPRIT generates test patterns by performing fault simulation on random patterns derived from nonuniformly distributed input signal probabilities. The system computes input signal probabilities that minimize a testability cost function. Using ESPRIT, we have observed orders-of-magnitude reduction in the number of random trials required to obtain a given fault coverage.