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Zhiping Wen 0001

dblp:11/2432 · also Zhi-ping Wen 0001 · DBLP profile ↗
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14ranked-venue papers
2as first author
6since 2021 · last 2025
0009-0004-4901-5681ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 9 · 2 first-author · 6 since 2021Systems, architecture and hardware · 4Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Reconfigurable computing and FPGAs · 57% Electronic design automation · 28% Hardware reliability and fault tolerance · 15%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA testing
0.532015
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only) · FPGA 2015
Coordinating routing resources for hex pips test in island-style FPGAs (abstract only) · FPGA 2014
A novel BIST approach for testing input/output buffers in FPGAs · FPGA 2009
Electronic design automation
hardware verification and test
0.322015
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only) · FPGA 2015
A novel BIST approach for testing input/output buffers in FPGAs · FPGA 2009
Reconfigurable computing and FPGAs › dynamic reconfiguration
partial reconfiguration
0.212015
A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only) · FPGA 2015
Hardware reliability and fault tolerance › radiation effects
single event effects
0.212015
300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only) · FPGA 2015
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.112009
A novel BIST approach for testing input/output buffers in FPGAs · FPGA 2009
Reconfigurable computing and FPGAs › FPGA architecture
SRAM-based FPGA
0.112015
300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only) · FPGA 2015

Methods — techniques the papers use, named apart from their topics

sorting algorithms · 0.2partial reconfiguration · 0.2partial-cascade pattern · 0.2coordinate system formulation · 0.2circle test structure · 0.2stuck-at fault detection · 0.1hard macro · 0.1
YearPublicationVenuePosition
2025 A rapid detection and quantification method for levee leakage outlets using drone infrared thermography and semantic segmentation
Renlian Zhou, Monjee K. Almustafa, Zhiping Wen 0001, Moncef L. Nehdi, Libing Zhang, Guang Yang 0048, Huaizhi Su 0001
Eng. Appl. Artif. Intell.3
2024 Deformation prediction based on denoising techniques and ensemble learning algorithms for concrete dams
Mingkai Liu, Zhiping Wen 0001, Huaizhi Su 0001
Expert Syst. Appl.2
2023 Spatiotemporal clustering analysis and zonal prediction model for deformation behavior of super-high arch dams
Wenhan Cao, Zhiping Wen 0001, Huaizhi Su 0001
Expert Syst. Appl.2
2022 MR and stacked GRUs neural network combined model and its application for deformation prediction of concrete dam
Zhiping Wen 0001, Renlian Zhou, Huaizhi Su 0001
Expert Syst. Appl.1
2022 Bi-criteria stability evaluation approach of gravity dam with pre-stressed cable reinforcement
Huaizhi Su 0001, Jinyou Li, Zhiping Wen 0001
Soft Comput.3
2022 An APPSO-SVM approach building the monitoring model of dam safety
Zhiping Wen 0001, Zhendong Fan, Huaizhi Su 0001
Soft Comput.1
2020 A kernel principal component analysis-based approach for determining the spatial warning domain of dam safety
Huaizhi Su 0001, Zhiping Wen 0001
Soft Comput.2
2019 An approach using Dempster-Shafer evidence theory to fuse multi-source observations for dam safety estimation
Huaizhi Su 0001, Zhiping Wen 0001
Soft Comput.3
2018 Nonprobabilistic Reliability Evaluation for In-Service Gravity Dam Undergoing Structural Reinforcement
abstract
Influenced by many factors such as material performance attenuation, structural defect repair, and reinforcement, the structural reliability of a gravity dam changes in different periods, which are called dynamic effects. Traditional methods are inclined to calculate and analyze the structural probability reliability from the random or fuzzy uncertain characteristics of parameters. However, in practice, it is difficult to obtain the probability distribution of uncertain parameters as well as the performance function, which is too nonlinear to be expressed. In addition, gravity dam failures are low probability events. Thus, a reliability calculation model and method for the gravity dam system considering dynamic effects under the practice of reinforcement are studied by integrating the theory of interval mathematics and nonprobability reliability. First, with the help of the monitoring data, and physical model and numerical simulation results of the gravity dam before and after the reinforcement, we establish a nonprobabilistic reliability (N-PR) calculation model for the gravity dam element and system based on the bounds of uncertain parameters and propose an inversion method for the bounds of uncertain parameters. Subsequently, by combining the response surface method with the central composite design technique, an N-PR index calculation method for gravity dams considering dynamic effects is developed. It turns out that the given model and method can effectively pave the way to avoid falling into the limitations of classical probabilistic reliability analysis of which the uncertain parameters require to be randomly changed and the results are highly sensitive to the parameters. In addition, it can better adapt to the characteristic of gravity dam performance function, which is too nonlinear to be expressed explicitly. When employing this method to analyze the reliability of gravity dam services, we are able to evaluate and predict the changing process and the trend of it more objectively, and have a closer look at the comprehensive influence and contribution of reinforcement to dam service reliability.
Huaizhi Su 0001, Jinyou Li, Zhiyun Guo, Zhiping Wen 0001
IEEE Trans. Reliab.4
2015 300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application (Abstract Only)
abstract
SRAM-based FPGAs have been widely used in space engineering. However, the configuration memory in SRAM-based FPGA is susceptible to the single event effects (SEE). It can disrupt the communication or control functions of the spacecraft. To mitigate SEE effects of the SRAM-based FPGAs used in space radiation environment, Beijing Microelectronics Technology Institute (BMTI) developed a 300 thousand gates Single Event Effect hardened SRAM-based FPGA -- BQVR300RH. The BQVR300RH employs Radiation Harden by Design (RHBD) technique. Hardened standard cell library based on Adaptive SRAM (ASRAM) structure is established. For especially sensitive and important resource, other assistant techniques are also adopted. The experiment results show that the BQVR300RH improved the anti-SEU characteristic a lot, compared with Xilinx 300 thousand gates space-grade SRAM-based FPGA (XQVR300). The SEU threshold of BQVR300RH is 19.06 MeV⋅cm2/mg. The anti-SEU characteristic improves three orders of magnitude than XQVR300. The improvement of anti-SEU behavior expands the usage of SRAM-based FPGA in aerospace applications. Currently, BQVR300RH has been used in space field in China.
Lei Chen 0010, Yuanfu Zhao, Zhiping Wen 0001, Xuewu Li, Yanlong Zhang, Huabo Sun
FPGA3
2015 A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only)
abstract
The programmability of an FPGA poses a number of challenges when it comes to complete and comprehensive testing of the FPGA itself. A large number of configurations must be downloaded into the FPGA to test the programmable sources. A great many methods were proposed to reduce the number of configurations to minimize the test time, but few of papers were focus on reducing single configuration time. This paper proposes a novel method to reduce more than 30% of the total configuration time based on partial reconfiguration technology and sorting algorithm. This method is implemented on a series of SRAM-based FPGAs. The experimental result shows that this method reduces 30%-45% of the total configuration time and can be generally applied to all SRAM-based FPGAs currently.
Xianjian Zheng, Lei Chen 0010, Zhiping Wen 0001, Yuanfu Zhao, Xuewu Li
FPGA4
2014 Coordinating routing resources for hex pips test in island-style FPGAs (abstract only)
abstract
The significance of FPGA test and the challenge of its increasing cost can never be ignored. In island-style FPGA architectures, hex lines are the principal interconnect resources. Testing hex lines and hex Programmable Interconnect Points (PIPs) have remained as the major technical difficulty in FPGAs test due to complex interconnect rules. Particularly, test in oblique direction of hex PIPs has rarely been addressed in previous studies. Towards this challenge, this paper for the first time proposes a coordinate system and formulates the interconnect rules of hex lines as mathematical equations. For hex PIPs in horizontal and vertical direction, an efficient circle test structure is formed by coordinate equations. For hex PIPs in oblique direction, the coordinate method is used to generate the partial-cascade pattern. The corresponding test vector is also generated, which ensures the ergodicity of hex PIPs in oblique direction. In addition to hex PIPs, hex lines are also covered without extra effort. Compared to previous researches, the configuration number for hex lines is decreased significantly. We evaluate this method on Xilinx XC2V1000, and experimental results show that our proposed method achieves 100% fault coverage for hex PIPs and can be generally applied to all mainstream island-style FPGAs with a similar interconnect structure currently.
Lei Chen 0010, Wenyao Xu, Yuanfu Zhao, Zhiping Wen 0001
FPGA5
2013 Multifractal scaling behavior analysis for existing dams
Huaizhi Su 0001, Zhiping Wen 0001, Bowen Wei
Expert Syst. Appl.2
2009 A novel BIST approach for testing input/output buffers in FPGAs
abstract
A novel Built-In Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series FPGAs using Hard Macro has been proposed in this paper. The proposed approach can completely detects single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been successfully implemented and verified on Xilinx Virtex series FPGA. Only total of eight configurations are required to completely built-in self test of the I/O buffers in Virtex series FPGA.
Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001
FPGA3