Multi-stage learning is an effective technique to invoke multiple deep-learning modules sequentially. This paper applies multi-stage learning to speech enhancement by using a multi-stage structure, where each stage comprises a self-attention (SA) block followed by stacks of temporal convolutional network (TCN) blocks with doubling dilation factors. Each stage generates a prediction that is refined in a subsequent stage. A fusion block is inserted at the input of later stages to re-inject original information. The resulting multi-stage speech enhancement system, in short, multi-stage SA-TCN, is compared with state-of-the-art deep-learning speech enhancement methods using the LibriSpeech and VCTK data sets. The multi-stage SA-TCN system's hyper-parameters are fine-tuned, and the impact of the SA block, the fusion block and the number of stages are determined. The use of a multi-stage SA-TCN system as a front-end for automatic speech recognition systems is investigated as well. It is shown that the multi-stage SA-TCN systems perform well relative to other state-of-the-art systems in terms of speech enhancement and speech recognition scores.

Speech enhancement is an essential component in robust automatic speech recognition (ASR) systems. Most speech enhancement methods are nowadays based on neural networks that use feature-mapping or mask-learning. This paper proposes a novel speech enhancement method that integrates time-domain feature mapping and mask learning into a unified framework using a Generative Adversarial Network (GAN). The proposed framework processes the received waveform and decouples speech and noise signals, which are fed into two short-time Fourier transform (STFT) convolution 1-D layers that map the waveforms to spectrograms in the complex domain. These speech and noise spectrograms are then used to compute the speech mask loss. The proposed method is evaluated using the TIMIT data set for seen and unseen signal-to-noise ratio conditions. It is shown that the proposed method outperforms the speech enhancement methods that use Deep Neural Network (DNN) based speech enhancement or a Speech Enhancement Generative Adversarial Network (SEGAN).

Energy consumption of customer premises equipment (CPE) has become a serious issue in the new generations of time-division multiplexing passive optical networks, which operate at 10 Gb/s or higher. It is becoming a major factor in global network energy consumption, and it poses problems during emergencies when CPE is battery-operated. In this paper, a low-energy passive optical network (PON) that uses a novel bit-interleaving downstream protocol is proposed. The details about the network architecture, protocol, and the key enabling implementation aspects, including dynamic traffic interleaving, rate-adaptive descrambling of decimated traffic, and the design and implementation of a downsampling clock and data recovery circuit, are described. The proposed concept is shown to reduce the energy consumption for protocol processing by a factor of 30. A detailed analysis of the energy consumption in the CPE shows that the interleaving protocol reduces the total energy consumption of the CPE significantly in comparison to the standard 10 Gb/s PON CPE. Experimental results obtained from measurements on the implemented CPE prototype confirm that the CPE consumes significantly less energy than the standard 10 Gb/s PON CPE.

Recent standardization efforts to reduce power consumption in optical access networks include the use of cyclic sleep modes to more effectively scale energy consumption with activity. This paper analyzes a probing-based cyclic sleep mode mechanism that is applied to the downstream of a passive optical network. The analysis studies the effectiveness of the sleep mode mechanism and provides explicit mathematical expressions for the power consumption and packet response delay in the optical network unit (ONU) at the customer premises, and the amount of buffered traffic per ONU in the optical line terminal at the central office. The analytical results are confirmed and complemented by numerical simulations, and used to provide guidelines for selecting sleep mode configuration parameters.

This paper presents an extremely compact, highly efficient hardware implementation of the Reed Solomon (RS) decoder. Such efficiency is of critical importance for the next generation of passive optical networks featuring bit rates of 10 Gb/s, high bit error rates and high cost sensitivity. RS codes are widely used for error correction in optical communication networks. The central element of a t-error correcting RS decoder is the key equation solver, which is the most time-critical stage in the RS decoder operation. It uses 2t equations to determine up to 2t unknown values. A key equation solver typically performs the Berlekamp-Massey (BM) algorithm or the Modified Euclidean (ME) algorithm. Hardware implementations of these algorithms usually include a large number of Galois Field (GF) multipliers needed to achieve the required throughput. This paper presents a scalable BM architecture and a scalable ME architecture that minimizes the number of GF multipliers by their higher utilization. This is achieved through efficient control that avoids idle cycles and also through optimal grouping of multipliers into parallel structures given the bit error distribution for the respective optical network. The major building block of this architecture is a compact, programmable GF processor (GFP) capable of high frequency operation.

A meshed network with N transport paths can be effectively protected against single link failures using network coding and protection cycles (p-cycles). This so called 1+N protection scheme provides instantaneous recovery from single link failures. The performance of this scheme has thus far been considered for a network with unit traffic demands, and the reported results were based on simulations. In this paper, we give an analytical upper bound on the required transport capacity for 1+N protection in full-meshed networks with unit traffic demands. Next, we consider networks with uniform and exponentially distributed traffic demands, and derive more realistic bounds for the achievable network performance of 1+N protection in full-meshed networks.We will show analytically that the gains decrease significantly relative to a unit-traffic demand distribution, independent of the protection mechanism used.

The sequence replacement technique converts an input sequence into a constrained sequence in which a prescribed subsequence is forbidden to occur. Several coding algorithms are presented that use this technique for the construction of maximum run-length limited sequences. The proposed algorithms show how all forbidden subsequences can be successively or iteratively removed to obtain a constrained sequence and how special subsequences can be inserted at predefined positions in the constrained sequence to represent the indices of the positions where the forbidden subsequences were removed. Several modifications are presented to reduce the impact of transmission errors on the decoding operation, and schemes to provide error control are discussed as well. The proposed algorithms can be implemented efficiently, and the rates of the constructed codes are close to their theoretical maximum. As such, the proposed algorithms are of interest for storage systems and data networks.

An error-resilient variable-length arithmetic code is presented whose codewords are represented by binary digits. The input sequence is partitioned in subsequences, each of which is individually encoded using an arithmetic coding scheme with an integrated bit-stuffing technique that restricts the number of consecutive ones in the output sequence. An all-ones sequence of fixed length is appended to serve as a sync marker when the codewords are concatenated. The bit-stuffing technique ensures that the sync markers do not occur anywhere except at the boundaries between the codewords. Expressions for the optimal choice of the marker length and the block length are derived. The performance of the proposed code is determined in terms of redundancy and error resilience. An upper bound on the average error rate is derived and its tightness is confirmed with computer simulations. The proposed code shows to significantly suppress the error rate at the expense of a minimum increase in redundancy.

Rapid acquisition of accurate crosstalk estimates is a core requirement for effective preceding in digital subscriber line (DSL) systems. It is shown that signal-to-noise ratio (SNR) reports provided by customer premises equipment (CPE) can be used to perform this task by "tuning" the precoder, i.e., iterating alternate steps of estimation and precoder adaptation. Such an approach has the advantage that it can be applied to legacy CPEs. Estimation algorithms are designed using techniques from stochastic control.

Integer codes, defined over integer rings, allow the correction of single cross errors with distance 1 in a signal point constellation on a two-dimensional lattice. Several construction methods support the construction of integer codes that give constellations that have a variety of shapes. In this paper, we characterize all constellations that can be obtained from a particular integer code. In particular, we determine those that minimize the average symbol energy. In addition, we evaluate the symbol error probability when using an integer code for coded QAM constellations.

We consider the class of integer codes that are capable of correcting single errors in a two-dimensional lattice (H. Morita et al., 2003). Integer codes, defined over integer rings, allow the correction of single errors with distance 1. In this paper, we extend our previous results (H. Morita et al., 2003). We will detail the derivation of an upper bound on the code size and give constructions that attain this bound. Next, several coding algorithms are presented that efficiently transform binary information into a sequence of symbols that are associated with signal points in a two-dimensional lattice. The proposed decoding algorithms can correct any single error with distance 1 in the given signal point constellation and restore the binary information. We will present a systematic technique to design signal point constellations that support the constructed integer codes and that are optimal in terms of the total Mannheim and Euclidean distance

A new class of DC-free codes of odd length is presented. The new codes, related to polarity-switch (PS) codes, make use of a redefinition of the running digital sum. The spectral efficiency of the new codes is determined, and it is shown that they provide better power suppression in the low-frequency region than classical PS codes

Methods are developed to effectively combine guided scrambling and maximum run-length limited codes in order to impose a guaranteed maximum run-length constraint. It will be demonstrated that the combination of guided scrambling and a well-chosen maximum run-length limited code may offer a sound trade-off between overall code rate and performance in terms of the probability of violating the channel constraints.

New methods are presented to protect maximum runlength-limited sequences against random and burst errors and to avoid error propagation. The methods employ parallel conversion techniques and enumerative coding algorithms that transform binary user information into constrained codewords. The new schemes have a low complexity and are very efficient. The approach can be used for modulation coding in recording systems and for synchronization and line coding in communication systems. The schemes enable the usage of high-rate constrained codes, as error control can be provided with similar capabilities as for unconstrained sequences.

We present advanced combinatorial techniques for constructing maximum runlength-limited (RLL) block codes and maximum transition run (MTR) codes. These codes find widespread application in recording systems. The proposed techniques are used to construct a high-rate multipurpose modulation code for recording systems. The code, a rate 16/17, (0,3,2,2) MTR code, that also fulfills (0,15,9,9) RLL constraints is a high-rate distance-enhancing code with additional constraints for improving timing and gain control. The encoder and decoder have a particularly efficient architecture and allow an instantaneous translation of 16-bit source words into 17-bit codewords and vice versa. The code has been implemented in Lucent read-channel chips and has excellent performance.

A new class of codes for frame synchronization is proposed. Commonly, the beginning of every fixed or variable-length frame is identified by a given contiguous sequence called a prefix. To avoid the occurrence of the prefix elsewhere in the frame, a prefix synchronizable code (PS-code) is used. PS-codes have the property that the prefix does not occur in any codeword or in any concatenation of codewords in any position other than the first position. The new codes, termed partial-prefix synchronizable codes (PPS-codes), use a fixed sequence of symbols that is interspersed with symbols that carry information. The contiguous sequence from the first fixed symbol to the last fixed symbol is called a "partial-prefix." Consequently, not one but a set of possible prefixes is used, and none of these prefixes is allowed to occur at any other than the first position of a codeword. The cardinality of PPS-codes is determined, and coding algorithms are proposed which have a computational complexity proportional to the length of the codewords. It is demonstrated that in comparison with PS-codes, PPS-codes have similar coding and prefix detection complexity, but they have a larger code size and have better error control capabilities.

Frame synchronization is traditionally achieved by inserting a given sequence periodically into the data stream. Here, a new method of synchronization is introduced in which the synchronization sequence is not contiguous, but is interleaved with the data symbols. The properties of these distributed sequences are investigated, and requirements are specified for detectability of these sequences when inserted in random data. Methods for constructing and searching for good sequences are presented. It is demonstrated that this new method reduces the probability of false synchronization over traditional methods in the presence of additive white Gaussian noise.

We present a systematic procedure for mapping data sequences into codewords of a prefix-synchronized code (PS-code), as well as for performing the inverse mapping. A PS-code, proposed by Gilbert (1960), belongs to a subclass of comma-free codes and is useful to recover word synchronization when errors have occurred in the stream of codewords. A PS-code is defined as a set of codewords with the property that each codeword has a known sequence as a prefix, followed by a coded data sequence in which this prefix is not allowed to occur. The largest PS-code among all PS-codes of the same code length is called a maximal prefix-synchronized code (MPS-code). We develop an encoding and decoding algorithm for Gilbert's MPS-code with a prefix of the form 11...10 and extend the algorithm to the class PS-codes of which the prefix is self-uncorrelated. The computational complexity of the entire mapping process is proportional to the length of the codewords.

EfJicient algorithms for testing the assembly of memory devices on a printed circuit board are presented. The algorithms provide for optimal fault detection and diagnosis of stuck-at faults and bridg-ng faults of memory interconnects with a small number of patterns. This small number of patterns makes application through boundaryscan feasible.