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M. Sultan Alam

dblp:11/316 · DBLP profile ↗
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4ranked-venue papers
4as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 61% Interconnection networks and networks-on-chip · 39%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › routing algorithms
fault-tolerant routing
0.021995
Routing in Modular Fault-Tolerant Multiprocessor Systems · IEEE Trans. Parallel Distributed Syst. 1995
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes · IEEE Trans. Parallel Distributed Syst. 1991
Hardware reliability and fault tolerance
fault-tolerant architecture
0.011991
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes · IEEE Trans. Parallel Distributed Syst. 1991
Hardware reliability and fault tolerance › reconfiguration
fault-tolerant reconfiguration
0.011991
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes · IEEE Trans. Parallel Distributed Syst. 1991
Hardware reliability and fault tolerance › reconfiguration
hypercube reconfiguration
0.011991
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes · IEEE Trans. Parallel Distributed Syst. 1991
Hardware reliability and fault tolerance › reconfiguration
spare allocation
0.011991
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes · IEEE Trans. Parallel Distributed Syst. 1991
Hardware reliability and fault tolerance › fault-tolerant architecture
fault-tolerant multiprocessor
0.011995
Routing in Modular Fault-Tolerant Multiprocessor Systems · IEEE Trans. Parallel Distributed Syst. 1995
Interconnection networks and networks-on-chip › network topology › static interconnection networks
hypercube and torus topologies
0.011995
Routing in Modular Fault-Tolerant Multiprocessor Systems · IEEE Trans. Parallel Distributed Syst. 1995
Interconnection networks and networks-on-chip
hypercube network
0.011991
An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes · IEEE Trans. Parallel Distributed Syst. 1991

Methods — techniques the papers use, named apart from their topics

worst-case routing analysis · 0.0reliability analysis · 0.0
YearPublicationVenuePosition
1995 Channel Multiplexing in Fault-Tolerant Modular Multiprocessors
M. Sultan Alam, Rami G. Melhem
J. Parallel Distributed Comput.1
1995 Routing in Modular Fault-Tolerant Multiprocessor Systems
abstract
In this paper, we consider a class of modular multiprocessor architectures in which spares are added to each module to cover for faulty nodes within that module, thus forming a fault-tolerant basic block (FTBB). In contrast to reconfiguration techniques that preserve the physical adjacency between active nodes in the system, our goal is to preserve the logical adjacency between active nodes by means of a routing algorithm which delivers messages successfully to their destinations. We introduce two-phase routing strategies that route messages first to their destination FTBB, and then to the destination nodes within the destination FTBB. Such a strategy may be applied to a variety of architectures including binary hypercubes and three-dimensional tori. In the presence of f faults in hypercubes and tori, we show that the worst case length of the message route is min {/spl sigma/+f, (K+1)/spl sigma/}+c where /spl sigma/ is the shortest path in the absence of faults, K is the number of spare nodes in an FTBB, and c is a small constant. The average routing overhead is much lower than the worst case overhead.
M. Sultan Alam, Rami G. Melhem
IEEE Trans. Parallel Distributed Syst.1
1991 Channel Multiplexing in Modular Fault Tolerant Multiprocessors
M. Sultan Alam, Rami G. Melhem
ICPP (1)1
1991 An Efficient Modular Spare Allocation Scheme and Its Application to Fault Tolerant Binary Hypercubes
abstract
Consideration is given to fault tolerant systems that are built from modules called fault tolerant basic blocks (FTBBs), where each module contains some primary nodes and some spare nodes. Full spare utilization is achieved when each spare within an FTBB can replace any other primary or spare node in that FTBB. This, however, may be prohibitively expensive for larger FTBBs. Therefore, it is shown that for a given hardware overhead more reliable systems can be designed using bigger FTBBs without full spare utilization than using smaller FTBBs with full spare utilization. Sufficient conditions for maximizing the reliability of a spare allocation strategy in an FTBB for a given hardware overhead are presented. The proposed spare allocation strategy is applied to two fault tolerant reconfiguration schemes for binary hypercubes. One scheme uses hardware switches to replace a faulty node, and the other scheme uses fault tolerant routing to bypass faulty nodes in the system and deliver messages to the destination node.>
M. Sultan Alam, Rami G. Melhem
IEEE Trans. Parallel Distributed Syst.1