This paper proposes a new testability analysis and test-point insertion method at the register transfer level (RTL), assuming a full scan and a pseudorandom built-in self-test design environment. The method is based on analyzing the RTL synchronous specification in synthesizable very high speed integrated circuit hardware descriptive language (VHDL). A VHDL intermediate form representation is first obtained from the VHDL specification and then converted to a directed acyclic graph (DAG) that represents all data dependencies and flow of control in the VHDL specification. Testability measures (TMs) are computed on this graph. The considered TMs are controllability and observability for each bit of each signal/variable that is declared or may be implied in the VHDL specification. Internal signals of functional modules (FMs) such as adders and comparators are also analyzed to compute their controllability and observability values. The internal signals are obtained by decomposing at the RTL large FMs into smaller ones. The calculation of TMs is carried out at a functional level rather than the gate level, to reduce or eliminate errors introduced by ignoring reconvergent fanouts in the gate network, and to reduce the complexity of the DAG construction. Based on the controllability/observability values, test-point insertion is performed to improve the testability for each bit of each signal/variable. This insertion is carried out in the original VHDL specification and thus becomes a part of it unlike in other existing methods. This allows full application of RTL synthesis optimization on both the functional and the test logic concurrently within the designer constraints such as area and delay. A number of benchmark circuits were used to show the applicability and the effectiveness of our method in terms of the resulting testability, area, and delay.

This paper proposes a new approach for designing a cost-effective on-chip Built-in Self-Test (BIST) generator through the use of Cellular Automata (CA) structures. The BIST generator thus designed is used to generate pseudorandom as well as deterministic test vectors. It is shown that no complex control logic is required to obtain either sequence. In addition, the resulting Test Vector Generator (TVG) is very efficient in terms of speed performances and is very regular and testable. Simulation of various benchmark circuits has given good results in terms of hardware size and test application time.

This paper proposes a new approach for designing a cost-effective, on-chip, deterministic, built-in, self-test generator. Given a set of precomputed test vectors (obtained by an ATPG tool) with a predetermined fault coverage, a simple test vector generator (TVG) is synthesized to apply the given test set in a minimal test time. To achieve this objective, cellular automata (CA) structures have been used in which the rule space is not limited to the linear rules commonly used in CA studies recently. Based on some new notations and new formulations of CA properties, two techniques are developed to synthesize such a TVG which is used to generate an ordered/unordered deterministic test vector set. The resulting TVG is very efficient in terms of hardware size and speed performance, and is very regular and testable. Simulation of various benchmark combinational circuits has given good results when compared to alternative solutions.>