A fully differential, power-efficient class AB Miller op-amp with accurate control of the output quiescent current is introduced. It can drive a wide range of resistive (200$\Omega$-1M$\Omega$) and capacitive loads (5pF-300pF). It has large dynamic and static current efficiencies of 8.6 and 7.9 and small-signal figures of merit higher than 7.4 for (1M $\Omega-200\Omega$) resistive load.

This paper presents the experimental evaluation of a Differential Pair with Active Loads (DPAL), designed and fabricated with a 0.5 μm CMOS process, when operated at a bias current of 1 nA and a power supply of 1 V. The objective is to verify that this circuit can properly perform analog functions while dissipating 1 nW. Therefore, experimental measurements that demonstrate its functionality, power dissipation and leakage currents are presented; the results indicate that it is possible to implement extreme low power analog circuits with this process.

A simple technique to greatly enhance the DC open-loop gain of a Miller op-amp is introduced here. It is based on the utilization of nested regulated cascode amplifiers. It uses conventional Miller compensation and does not increase the supply voltage. The proposed scheme has a DC open-loop gain Figure of Merit FoMAOLDC=24,614kV/V.pF.MHz/μWatt. It is especially appropriate for utilization in modern deep sub-micrometer CMOS technologies with low intrinsic gain.

An ultra low voltage low power AC coupled amplifier operating with supplies as low as ±0.18 V in 180 nm CMOS technology and a power dissipation of 0.15 μW is introduced. It has digitally programmable gain in the range from 1 to 15 and true constant bandwidth from 0.7 Hz to 2 kHz that is independent on gain. Experimental results from a test chip validate the proposed circuit. Additionally, simulations of the same PGA in 130 nm CMOS technology show that the proposed scheme operates with ±0.08 V supplies, total power dissipation of 0.07 μW and true constant bandwidth from 7.5 Hz to 8 kHz.

The present work proposes a new current-mode, programmable Kerwin Huelsman Newcomb (KHN) filter suitable for very low frequency processing. The proposed implementation, developed with only six current mirrors and two large-valued, programmable active resistors, solves some of the more challenging problems of low frequency filtering. HSPICE simulation results using BSIM3.3 models for a 0.5-μm CMOS technology, are shown. Center frequencies in the range of 12.4Hz-33Hz, total harmonic distortion less than 1%, and static power consumption of 1.05mW, were observed.

This paper proposes two new offset compensation techniques based on unbalanced polarization. They are based on the use of transistors operating in subthreshold to sense the DC offset and to use this value to generate unbalanced bias currents. These strategies do not degrade the frequency response and have smaller cost in area, power consumption and complexity than other offset compensation techniques. As a proof of concept, two low-voltage, current-mode multipliers and dividers using these strategies and designed in a 0.5 /spl mu/m CMOS process are presented.

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The array median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on transconductance comparators to speed their time response, while the time delay is implemented using all-pass filters. Both circuits allow modular expansion for the implementation of large sized median filter array processors. In addition, a fast novel technique for parallel image processing is presented. It is shown that an image of 91/spl times/81 pixels is processed in less than 30 /spl mu/S using an array of high-speed analog processors. Experimental results of a test chip prototype in 2 /spl mu/m CMOS technology MOSIS process are presented.