We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. The effect of our method is verified experimentally using 8 benchmark circuits with a 0.6 m standard cell library. Our method reduces the power dissipation from the minimum-sized circuits further by 9.8 % on average and 23.0 % maximum. We also verify that our method is effective under manufacturing variation. 1

A new memory-based architecture for real-time image convolution with variable kernels is proposed. The architecture exploits the highest possible bandwidth inherent in memory and achieves the fine-grain parallelism of computations inside the memory. Unlike existing approaches, the architecture ensures convolution with very large kernels under the real time constraints of video applications. It does not require external memory banks or large I/O count and features single chip VLSI implementation.

We propose a low bit-rate coding algorithm for wireless communication based on multi-stage hierarchical vector quantization, motion compensation and differential pulse code modulation. Our method adapts bit allocation to spatial and temporal correlation. Conventional schemes based on the discrete cosine transform (DCT) need a large amount of computation on both encoding and decoding. On the other hand, our proposed method consists of addition, subtraction and shift operation. It does not use multiplication. It can decode in real time on a conventional serial processor. Encoding by vector quantization (VQ), however, consumes a large amount of computation. We developed a new LSI to accelerate VQ. Our scheme can send 10 frames of QCIF video sequences through a 29.2 kbps line. The quality of reconstructed image is over 30 dB.

We present a gate delay model of CMOS logic gates driving a CRC n load for deep sub-micron technology.Our approach is to repIace series-parallel connected MOSFETS to an equivalent MOSFET and calculate the output waveform by an analytically derived formula.We present a MOSFET drain current model improved from the n-th power law hlOS~T model to represent the characteristic of the equivalent inverter accurately, The accuracy of our gate delay model is evaluated in several gates under various conditions of input transition time and CRC parameters.The maximum error is less than 10.3% in the experiments.Our approach will contribute to fast and accurate estimation of circuit speed under various supply voltage, which will enable us to optimize the circuit speed and power dissipation.

We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and device a gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 µm standard cell library. Gate sizing reduces the number of glitch transitions by 38.2 % on average and by 63.4 % maximum. This results in the reduction of total transitions by 12.8 % on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4 % on average and by 15.7 % maximum further from the minimum-sized circuits.

We present a parameter-extraction method that is applicable to many metal-oxide-semiconductor field-effect-transistor (MOSFET) models. A simple intermediate model is introduced to eliminate model dependency of parameter estimation for numerical optimization techniques. The process of the parameter estimation is decomposed into two parts: extraction of parameters of the intermediate model and transformation of the intermediate parameters into target model parameters. Only the latter part should be devised to accommodate new MOSFET models, which may be mostly identical with that for another model. We have integrated the method onto an extraction system, and verified that the method is effective for parameter extraction of major SPICE models.

We propose a memory-based parallel processor for vector quantization, called a functional memory type parallel processor for vector quantization (FMPP-VQ). It accelerates the nearest neighbour search of vector quantization. All distances between an input vector and reference vectors in a codebook are computed simultaneously in all PEs. The minimum value of all distances is searched in parallel. The nearest vector is obtained in O(k), where k stands for the dimension of vectors. An LSI including four PEs has been implemented. It operates at 25 MHz clock frequency.

We have developed a current mode cyclic analog-to-digital converter using a 0.8 /spl mu/m CMOS process. Our circuit structure makes it possible to construct the converter without any precise analog components, hence, it is well compatible with submicron processes. The fabricated circuit has an area of 0.014 mm/sup 2/ and performs 8-bit resolution at a sampling rate of 40 kHz and average power dissipation of 370 /spl mu/W at 4 V supply voltage.

This paper proposes a novel array architecture for full-search block matching motion estimation. The design efforts are focused on transforming the array computation in a way that minimizes the memory and I/O costs while satisfying the highest throughput requirements. Compared with the existing architectures, this one ensures feasible solutions for the HDTV picture format with twice lower memory requirements, minimal I/O pin count and 100% processor utilization. The architecture features regular and simple interconnects and is quite suitable for VLSI implementation.

This paper introduces a new gate sizing approach for area and power optimization considering path sensitization. The approach selects a set of long paths from a combinational circuit by means of a performance optimization oriented heuristic path selection approach. The longest sensitizable path delay of the circuit can be restricted within the specified delay limit if we set the specified delay limit on these paths in an LP based iterative gate sizing process. Since the approach get rid of unnecessary delay constraints on long false paths, results with smaller circuit area or power dissipation is expected. Experiments on benchmark circuits show that the proposed approach can substantially reduce the circuit area and power dissipation by considering path sensitization for some false path dominated circuits.

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No abstract available.

This paper introduces a new gate sizing approach with accurate delay evaluation. The approach solves gate sizing problems by iterating local sizing results from linear programming within mall variable ranges of gate sizes. In each iterative step, variable ranges of gate sizes are updated according to the result from a previous step. Solutions with accurate delay evaluation which consider input signal slopes and separately evaluate rising and falling delays are obtained after several iterative steps. A speedup technique is used to pick out gates actually involved in each local sizing step so as to reduce CPU time. Experiments on sample circuits show that our approach can provide solutions with smaller circuit area than conventional approaches for the same circuit delay or provide solutions under tight delay constraints where conventional approaches can nor reach. Moreover, our approach is faster than the conventional approaches for most circuits, especially under loose delay constraints.

Nowadays, the addition of specific hardware to CAD or DA applications has been received by the engineering community. Specially, Content Addressable Memory (CAM) is in the limelight because of its fast processing capability. In this paper, we propose a new algorithm and reformed CAM to deal with the sorting problem that always takes the bulk of the execution time in some applications such as design-rule checking. They can effect an 80% reduction in retrieval times.

The design of portable battery-operated systems requires multiplication circuits of low switching activity. This paper studies multiplication algorithms, sign extension methods, adding structures, resource sharing and component schematic alternatives from the point of decreasing the total number of logic transitions in the target multiplication circuit. Experiments show, that by utilizing the signed-digit encoding scheme, modified sign extension technique, 4-2 adding compressors and swing restored transistor path logic, a twice as low switching activity can be achieved.

As sub-micron design rules are utilized for IC fabrication, wiring is becoming an important issue in the register-transfer synthesis of high-speed application-specific integrated circuits. This paper proposes a new algorithm that incorporates performance-driven placement in module selection phase of the synthesis. The algorithm not only efficiently exploits multiple module implementations in the design library, but also finds the module placement which minimizes wiring delay. Experimental results on a practical size example show that considering both module and wiring issues, the algorithm is able to improve the design performance more than 20%.

We present a branch-and-bound placement technique for building block layout that effectively searches for an optimal placement in the whole solution space. We first describe a block placement problem and its solution space. Then we explain branching and bounding operations designed for the placement problem. Constraints on critical nets and/or the shape of a resulting chip can be taken into account in the search process. Experiments reveals that the number of blocks the method can manage is around six if the whole solution space is explored. For a problem which contains more blocks than the limit, we decompose the problem hierarchically and apply the method to each subproblem. The results for standard benchmark examples and a comparison with those of other systems are given to demonstrate the performance of the method.

A technique is presented for functional information extraction, which is the transformation of design descriptions from the logic circuit level to the functional level. The authors have developed a functional information extraction system, FINES, which can deal with both logic functions and arithmetic functions. The technique has made use of the characteristics of the functions in order to perform function extraction independent of the circuit structures.>