This paper describes the capacitorless 1-transistor (1T) DRAMs exploits the floating body (FB) effect of Fully depleted (FD) SOI devices, where the transistor body is used as a charge storage node. A novel three-tier, 3D, 1T embedded DRAM is presented that can be vertically integrated with the microprocessor achieving low cost, high density on-chip main memory. A 394Kbits test chip is designed and fabricated in a 0.15um fully depleted SOI CMOS process. The measured retention time under holding conditions is higher than 10ms. In the continuous read mode, every read should be followed by a refresh. The test chip is designed to work with an access time of 50ns and operates at 10MHz.

Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 m fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.

Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or permitting multicore access to shared memory using a large number of vertical vias between tiers in the stack, for ultrawide bit path transfer of data and address information to and from various levels of cache. Although a limited amount of parallel access is possible using conventional two-dimensional (2-D) chip memory-processor approaches, 3-D memory-processor stacking greatly extends this to much larger capacity memories. We evaluate high-clock-rate processors as well as shared memory processors with a large number of cores. Various architectural design options to reduce the impact of the memory wall on the processor performance are explored and validated through simulations. Certain architectural features can be implemented in a 3-D chip, such as an ultrawide, ultrashort vertical bus with low parasitic resistance and the elimination of conventional electrostatic discharge, and packaging parasitics required in multiple package 2-D solutions. The objective is to reduce the clocks per instruction figure of merit for high clock speeds in order to deliver significant performance levels. High-clock-rate processors can be designed with SiGe heterostructure bipolar transistors to obtain processors operating on the order of 16 or 32 GHz.

Forty years ago Gene Amdahl published a figure of merit for parallel computation, which proved extremely controversial. The controversy still rages today, although those that have looked closely at this figure of merit conclude that it is correct, but perhaps misinterpreted. In this paper we will look at a small variation on that law that suggests computer designers should take a closer look at two emerging technologies, SiGe HBT BiCMOS and 3D chip stacking. We may be overlooking a way to continue the clock race, and in so doing accomplish better parallelism.

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

FPGAs have been a popular topic among electrical engineers for over a decade. Modern FPGAs are denser, faster and use less power compared to PLD and CPLD. This paper presents a high speed FPGA that operates in the gigahertz range. An improved reconfigurable circuit is described. State-of-the-art IBM SiGe BiCMOS technology is used to realize this high speed FPGA. A measurement on a fabricated chip proves that this FPGA is capable of operating at 11 GHz, a SONET OC-192 standard, for optical applications.

A major impediment to the continuation of Moore's Law in the years to come is the performance of interconnections in ICs at high frequencies. Microprocessors are using a greater portion of their clock cycle charging and discharging interconnections. Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) provide a fast track technology for the exploration of the effect of interconnections on high-speed computer design. Industry has pursued low-k dielectrics to decrease wire capacitance. Cu metallization has been used to reduce wire resistance which becomes important as the wire dimensions are scaled down. These are not the only issues for high-frequency interconnections. Some other high-frequency issues include coupling, transmission line propagation, skin effects, and dielectric and substrate loss. These phenomena cause signal attenuation, noise, and dispersion in addition to delay. In the limit of zero device delay, interconnection delay will remain in addition to these problems. Wire shortening has been possible using more layers of interconnections, but this approach may be reaching its limit. An unconventional approach, three-dimensional (3-D) integration, attempts to shorten wiring through increased circuit component placement flexibility. The approach considered here for 3-D integration uses wafer-to-wafer aligning and bonding, wafer thinning and deep, high-aspect-ratio Cu via formation. This provides an intimate interconnection between CPU components and an extremely wide path to memory that would be infeasible in conventional or multichip module packaging. This combination of SiGe HBT BiCMOS and 3-D chip stack technologies enables small computing engines in the 16-32-GHz range.

This paper describes the implementation of a large scale SiGe FPGA that serves as a high speed FPGA test platform. In the FPGA core, 20 x 20 building blocks (Basic Cells) are used to implement logic applications. This chip contains 106 devices including SiGe NPNs and MOSFETs. This chip is fabricating with the IBM SiGe 7HP process with cut off frequency of 120GHz. The target running frequency of this FPGA is 10GHz. Clock repeaters are added for improved clock distribution. A test circuit whose building block cell runs up to 10GHz is fabricated and measured by the same process. Future work and some potential applications of the SiGe FPGA are also described.

This paper describes the implementation of a scalable SiGe FPGA that serves as a high speed FPGA test platform. A new configurable block (Basic Cell) has been evolved from the Xilinx 6200 specification, and is designed to perform in the gigahertz range. Two chips, a 4:1 multiplexer and 1:4 demultiplexer, were designed using the IBM SiGe 7HP process. The two designs can process 10 Gbps data streams.

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuit's performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing.

The low operating speed of current CMOS Field Programmable Gate Arrays (FPGAs), i.e., 10-220 MHz, has prevented their use in high-speed digital applications. With the advent of IBM Silicon Germanium (SiGe) 7HP technology, designers have been able to design FPGAs operating in the gigahertz range. This paper is going to elaborate on the implementation of a 4-bit ripple-carry full adder (FA) on the new SiGe FPGA with new architectures and a novel power management strategy. The 1-bit FA can be realized in three Configurable Logic Blocks (CLBs). Apart from these, the FA can operate in multiple modes: FAST, NON-CRITICAL, SLOW and OFF. The propagation delays of the 1-bit FA and 4-bit ripple-carry FA are 240 ps and 675 ps respectively in the FAST mode. All the simulation and layouts were done using Cadence 4.4.6 and IBM SiGe 7HP design kit version 1.1.1.0.

The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated Circuits (IC) such as microprocessors have been entering the giga-hertz operating frequency range, various speed related roadblocks have become increasingly difficult to overcome. The migration to smaller devices has raised serious challenges. The major impediment to fulfill Moore's Law effectively in the years to come is increasingly becoming the interconnect. ICs are using a greater fraction of their clock cycles charging interconnect wires. IC interconnect related speed degradation has stimulated much research effort in the area of low dielectric constant materials. A relatively novel approach, wafer scale 3-dimensional (3D) integration attempts to by-pass the large wire parasitics by shortening wires. This paper is going to elaborate on a 3D microprocessor test vehicle. We intend to demonstrate the speed advantages, which may be derived from 3D integration, through a combination of fabrication, testing and simulation.

A high speed, low power FPGA design is presented in this paper. This gigahertz FPGA design has an improved XC6200 structure. Redundant multiplexers are eliminated from critical signal path to enhance the performance of the previous design. By balancing between the power consumption and performance, the simulated clock rate is from 5 GHz to 20 GHz and the power consumption is from 4 mW to 12 mW per single cell in the IBM 7HP SiGe HBT BiCMOS process.

The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnect-capacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-/spl kappa/ polymeric dielectrics used in high-performance ICs. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs-GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or varactors. A novel, fully symmetric exclusive-OR (XOR) circuit was developed which uses product pairs and emitter-coupled logic. To achieve the highest performance possible, the critical path is symmetric and special physical design techniques were developed to promote matched-capacitance. The maximum measured frequency was 13.66 GHz. The chip occupies 1.9 mm/spl times/1.6 mm and dissipates 2.45 W at a supply voltage of -6.0 V. With a measured frequency range from 1.25 to 13.66 GHz, this circuit has the widest bandwidth reported in the literature for any VCO, digital or analog.

In many sonic imaging applications the echos resulting from wall reflection, scatter transmission, and resonance due to internal wall reverberation are significant sources of distortion. These echos and reverberation produce many false target images which are usually indistinguishable from true target images using simple ad hoc correlation techniques. Of course, propagation through a linear reverberant medium may be modeled by a transfer function or linear filter for which an inverse exists. Unfortunately, this filter is not known a priori and it must be estimated from stochastic data. The sources of interest here are assumed to emit random trains of pulses. The reverberant pulse responses usually overlap in time precluding discrimination of the individual pulses. Such pulse trains are characteristic of acoustic emission (AE) signals generated during crack formation in solids. The purpose of this study is to devise a scheme to deresonate the signals received at individual array elements using minimal information about the source signal itself and its power spectrum. This will be accomplished with the use of homomorphic deconvolution.

Recently there has been interest in applying the results of digital filter design theory to the optimization of the beam forming pattern of antenna arrays. The techniques employed usually involve minimax criteria for side lobe suppression. Certain applications require focused operation in order to make use of the near field for imaging. Nonuniform array element spacings have been successfully employed to reduce side lobes in phased arrays and to minimize the number of elements. Presented here will be a combination of nonuniform spacing, focusing, and element shading using some optimizing window designs to form a narrow center beam with very good side lobe suppression. The treatment is unique in that it explicitly incorporates the effects of focusing in the optimization procedure.