Retrieval-augmented generation (RAG) systems rely on large-scale embedding search. However, the growth of corpora and the demand for real-time queries expose the memory capacity and bandwidth limitations of DRAM-centric architectures. To address this challenge, we adopt CXL memory in conjunction with cluster-scale RAG deployments and optimize the system in terms of performance, latency and cost efficiency. Our design leverages state-of-the-art CXL memory devices and platforms with memory management policies such as weighted interleaving and tiering between DRAM and CXL memory. In comparison with a DRAM baseline, our system archives 20% higher vector search performance and 43% lower LLM time-to-first token (TTFT), demonstrating clear end-to-end performance benefits. Moreover, in the context of overall system efficiency, we observed up to 20% and 42% improvement in power efficiency (QPS/Watt) and cost efficiency (QPS/$), respectively. These results demonstrate that, despite the relatively high latency of CXL memory, memory management policy-level optimization enable CXL memory to serve as a first-class memory resource in cluster-based RAG systems.

Backlight systems dominate the power requirements of battery-operated hand-held devices with color thin-film transistor (TFT), liquid crystal displays (LCDs). We introduce dynamic luminance scaling of the backlight with appropriate image compensation. Dynamic backlight luminance scaling (DLS) keeps the perceived intensity or contrast of the image as close as possible to the original while achieving significant power reduction. DLS compromises quality of image between power consumption, which fulfills a large variety of user preferences in power-aware multimedia applications. DLS saves 20% to 80% of power consumption of the backlight systems while keeping a reasonable amount of image quality degradation.

Memory systems are dominant energy consumers, and thus many energy reduction techniques for memory buses and devices have been proposed. For practical energy reduction practices, we have to take into account the interaction between a processor and cache memories together with application programs. Furthermore, energy characterization of memory systems must be accurate enough to justify various techniques. In this article, we build an in-house energy simulator for memory systems that is accelerated by special hardware support while maintaining accuracy. We explore energy behavior of memory systems for various values of the processor and memory clock frequencies and cache configuration. Each experiment is performed with 24M instruction steps of real application programs to guarantee accuracy.The simulator is based on precise energy characterization of memory systems including buses, bus drivers, and memory devices by a cycle-accurate energy measurement technique. We characterize energy consumption of each component by an energy state machine whose states and transitions are associated with the dynamic and static energy costs, respectively. Our approach easily characterizes the energy consumption of complex SDRAMs. We divide and quantify energy components of main memory systems for high-level reduction. The energy simulator enables us to devise practical energy reduction schemes by providing the actual amount of reduction out of the total energy consumption in main memory systems. We introduce several practical energy reduction techniques for SDRAM memory systems and demonstrate energy reduction ratio over the SDRAM memory systems with commercial SDRAM controller chipsets. We classify the SDRAM memory systems into high-performance and mid-performance classes and achieve suitable system configurations for each class. For instance, a typical high-performance 32-bit, 64 MB SDRAM memory system consumes 19.6 mJ, 33.8 mJ, 35.4 mJ, and 37.0 mJ for 24M instructions of an MP3 decoder, a JPEG compressor, a JPEG decompressor, and an MPEG4 decoder, respectively. Our reduction scheme saves 12.7 mJ, 15.1 mJ, 15.5 mJ, and 14.8 mJ, and the reduction ratios are 64.8%, 44.6%, 43.8%, and 40.1%, respectively, without compromising execution speed.

In this paper, we introduce a precise energy characterization of SDRAM main memory systems and explore the amount of energy associated with design parameters, leading to energy reduction techniques that we are able to recommend for practical use.

An LCD (Liquid Crystal Display) is a standard display device for hand-held embedded systems. Today, color TFT (Thin-Film Transistor) LCDs are common even in cost-effective equipments. An LCD display system is composed of an LCD panel, a frame buffer memory, an LCD and frame buffer controller, and a backlight inverter and lamp. All of them are heavy power consumers, and their portion becomes much more dominant when running interactive applications. This is because interactive applications are often triggered by human inputs and thus result in a lot of slack time in the CPU and memory system, which can be effectively used for dynamic power management.