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Noritake Yonezawa

dblp:11/4221 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › high-level synthesis › scheduling
dataflow graph scheduling		 0.011994
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation
high-level synthesis		 0.011994
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994
Electronic design automation › high-level synthesis
scheduling		 0.011994
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994

Methods — techniques the papers use, named apart from their topics

hierarchical reduction · 0.0bottom-up transformation · 0.0
YearPublicationVenuePosition
1994 A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach
abstract
A new scheduling algorithm for dataflow graphs with nested conditional branches is presented. The algorithm employs a bottom-up approach to transform a dataflow graph with conditional branches into an "equivalent" one that has no conditional branches. A schedule is then obtained for the latter, using a conventional scheduling algorithm, from which a schedule for the former is derived. Our approach is particularly effective when there is a large number of nested conditional branches in a dataflow graph.>
Taewhan Kim 0001, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu 0001
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2