As process technologies continue to shrink, and feature demands continue to increase, more and more capabilities are being pushed into smaller and smaller packages. But are we finally reaching the point where power density limitations make this trend no longer sustainable? What advanced techniques are in use today, and on the horizon, to address this? Are we limited only to hardware techniques, or can these power limitation issues be addressed with smarter software development? And how do we handle verification of these complex implementations? This paper explores possible methods for improving the ";power capacity"; of power sensitive designs.

The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by different compression techniques, to enable the selection of the right set of design and test parameters. This paper highlights the available solution space for compression based designs and discusses the various parameters which result in test tradeoffs. The discussion is supported with elaborate experimental data. Through them, the paper offers an insight into the solution space of compression techniques and makes resulting recommendations.

Summary form only given. Dr. Gordon E. Moore's Law - integration's capacity doubles every two years - is under server pressure. Leakage power is the major factor in the challenge to keep Moore's Law alive and well. As process technologies continue to shrink, and feature demands continue to increase, more and more capabilities are being pushed into smaller and smaller packages. But are we finally reaching the point where power density limitations make this trend no longer sustainable? The test environment has long been known to be more severe power wise than the functional environment. To that end, a number of new approaches need to be taken in the test area to control not only scan in power but also the capture power. What advanced techniques are in use today, and on the horizon, to address this? Are we limited only to hardware techniques, or can these power limitation issues be addressed with smarter software, such as automatic test pattern generation tools? And how do we handle verification of these complex implementations? How do these new demands affect our ability to compress test time and test data volume? This paper explores possible methods for improving the "power capacity" of power-sensitive design from both the functional and test perspectives.

Testing for small delay defects requires ATPG-FS tools to understand timing information of the design such that transition delay faults can be detected along longer paths. In this paper, timing information is analyzed for use in test automation tools to test for small delay defects. Fundamentals of static timing analysis are analyzed with regard to test. This paper concludes that Signal Integrity information can be ignored by test automation tools when timing information is used to guide ATPG tools towards longer paths. This paper also shows that a lack of understanding of clock trees in the long path ATPG algorithm leads to incorrect results.

Scan is widely accepted as the basis for reducing test cost and improving quality, however its effectiveness is compromised by increasingly complex designs and fault models that can result in high scan data volume and application time. The authors present a scan compression method designed for minimal impact in all aspects: area overhead, timing, and design flow. Easily adopted on top of existing scan designs, the method is fully integrated in the scan synthesis and test generation flows. Data and test time compressions of over 10times were obtained on industrial designs with negligible overhead and no impact on schedule.

Design has never been simple, but at 130 nm and below, and definitely at 90 nm, it is becoming increasingly difficult. Process and lithography issues continue to drive our advance to new technology nodes. Due to the effects of scaling, defect mechanisms are no longer easily identified with single "stuck at" fault models but rather are demanding far more complex and challenging solutions. For example, shorts are now being extracted from the physical layout of a design, with special tests being created to detect them. But this is just the beginning; delay testing of all transition faults is now a new objective of design for testability (DFT). New demands are being made on design to not only create the correct function and help with testing but also to help yield ramp-up. The areas of design for manufacturing (DFM) and design for yield (DFY) are now also talking hold as new requirements for design. Manufacturing and test are beginning to develop an even stronger relationship due to the close interconnection between yield ramp-up and diagnostics, which are supported by DFT structures included in the design

Recent test-cost reduction methods are based on controlling the initial state (seed) of a pseudo-random pattern generator (PRPG) so that deterministic values are loaded in selected scan cells. Combined with an unload-data compression technique, PRPG seeding reduces test data volume and application time. This paper presents a method of mapping each scan load to multiple PRPG seeds, computed so that test pattern count, data volume, and, therefore, test cost are minimized. This method also allows smaller and fewer PRPGs, reducing the area overhead of test-compression circuitry. The results on deep-submicron industrial designs, show significant test cost reduction when this method is applied with either X-tolerant or X-free unload-data compression

This paper extends the reconfigurable shared scan-in architecture (RSSA) to provide additional ability to change values on the scan configuration signals (scan enable signals) during the scan operation on a per-shift basis. We show that the extra flexibility of reconfiguring the scan chains every shift cycle reduces the number of different configurations required by RSSA while keeping test coverage the same. In addition a simpler analysis can be used to construct the scan chains. This is the first paper of its kind that treats the scan enable signal as a test data signal during the scan operation of a test pattern. Results are presented on some ISCAS as well as industrial circuits.

In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic models: the Williams-Brown (WB) model and the Mercer-Park-Grimaila-Dworak (MPGD) model. In the WB-model, the defect coverage is replaced by the n-detection transition fault coverage. We first demonstrate that both logic models may fail to predict the detection of statistical timing defects. Then, we propose an improved WB model based upon selection of the hard-to-detect transition faults. We show that, by selecting a proper subset of the hard-to-detect transition faults, the detection behavior of these faults can correlate well to the detection behavior of statistical timing defects. We explain our findings through statistical delay defect injection and simulation, and report results based upon various benchmark circuits.

In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

In this paper the solution the industry is driving towards for manufacturing test of SoCs is described. The quality of test for every core that is integrated on the chip is very important to the overall quality of the SoC. In this paper a method for evaluating the quality needs of an embedded core relative to the embedded environment is presented. Due to the partitioning of the test data and the increased stress in quality for individual designs the test application time is increasing. This paper presents the problems associated with test application time with SoCs.

In conventional delay testing, the test clock is a single pre-defined parameter that is often set to be the same as the system clock. This paper discusses the potential of enhancing test efficiency by using multiple clock frequencies. The intuition behind our work is that for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out the potential defective chips. Then, by using a smarter test clock scheme and combining with a second set of AC delay patterns, the overall quality of AC delay test can be enhanced while the cost of including the second pattern set can be minimized. We demonstrate these concepts through analysis and experiments using a statistical timing analysis framework with defect-injected simulation.

Logic BIST is about to become a more main stream test method for IC testing. In some flows when a failure is encountered the IC is diagnosed to determine the cause of the failure. Diagnosing fails in Logic BIST is significantly different from that in a stored pattern test methodology. The first step is to determine the failing pattern or interval among the many patterns that were applied. Today this involves a binary search of the tests that were applied with Logic BIST. In this paper we improve on this binary search strategy to reduce the time taken to isolate the failing patterns by orders of magnitude.

Solving a system of linear equations has been widely used to compute seeds for LFSR reseeding to compress test patterns. However, as chip size is growing, solving linear equations requires a large number of computations that is proportional to n3. This paper proposes a new scan chain architecture and algorithm so that the order of computation is proportional to the number of scan cells in a chip. The new architecture is a methodology change that does not require complex Design-For-Testability (DFT) as proposed in the previous techniques. Instead of solving linear equations, the proposed new seed computation algorithm topologically determines seeds for test vectors. The compression ratio might be slightly lower than the other approaches, but the proposed approach can handle larger designs in a reasonable amount of time. Computation analysis shows that, for 1 million scan cell design, if we assume it takes 1 msec for the proposed technique to compute seeds, it would take more than 14 minutes for other techniques that solve linear equations.

In conventional delay testing, two types of tests, transition tests and path delay tests, are often considered. The test clock frequency is usually set to a single pre-determined parameter equal to the system clock. This paper discusses the potential of enhancing test effectiveness by using multiple test sets with multiple clock frequencies. The two intuitions motivating our analysis are 1) multiple test sets can deliver higher test quality than a single test set, and 2) for a given set of AC delay patterns, a carefully-selected, tighter clock would result in higher effectiveness to screen out potentially defective chips. Hence, by using multiple test sets, the overall quality of AC delay test can be enhanced, and by using multiple-clock schemes the cost of adding the additional pattern sets can be minimized. In this paper, we analyze the feasibility of this new delay test methodology with respect to different combinations of pattern sets and to different circuit characteristics. We discuss the pros and cons of multiple-clock schemes through analysis and experiments using a statistical delay evaluation and delay defect-injected framework.

The industry is scrambling to prevent a potential explosion in nanometer technology test cost where the cost to test a device is closing in on the cost to manufacture it. Across the test industry, entire methodologies are being readdressed, tester costs are being scrutinized, and test vector count is being reduced. In this paper, a new concept is presented that allows for lowering the cost of test by utilizing the tester resources more efficiently. The solution presented brings together an existing concept of being able to reconfigure scan chains with methods that allow the same test pattern data to be applicable for all configurations. A data model is created to emphasize the use of such technology. The concepts developed in this paper are compatible with other test cost reduction methods.

Typically the DFT features are decided during the design and remain fixed after the design is completed. This makes a device testable only on ATEs, which can satisfy the test requirements for that chip. If such an ATE is not available then the IC either cannot be fully tested, or ATE resources are wasted when it is designed for less capabilities. This paper presents a methodology that builds on the tester retargetable pattern technology for testing ICs on testers with different pin capabilities. Such a capability would be an essential element in reduced pin-count (multi-site) testing. The interfacing needs between the Test Automation World and the Tester Environment are also developed in this paper.

Originally developed decades ago, logic built-in self-test (BIST) evolved and is now increasingly being adopted to cope with rapid growth in design size and complexity. Compared to deterministic pattern test, logic BIST requires many more test patterns, and therefore, increased test time unless many more internal scan chains can be shifted in parallel. To match this large number of scan chains, the width of the signature analyzer would have to be enlarged, which would result in large area overhead and signature storage space. Instead, a combinational space-compactor is inserted between the scan chain outputs and the signature analyzer inputs. However, the compactor may deteriorate the ability to test and diagnose the design. This paper analyzes how compactors affect test and diagnosis and shows that compactors can be designed to actually improve the testability of certain faults, while providing full diagnosis capability. Algorithms that allow automated design of optimal compactors are presented and results are discussed.

It is becoming evident that testability must be addressed throughout the entire design process. To successfully meet all the design goals of today's and tomorrow's enormously complex devices, swift convergence of function, timing, area and power requirements must be simultaneously accompanied by new test tools that enable rapid, predictable and repeatable DFT closure. Achieving successful DFT closure requires that RTL designers and DFT engineers work in concert on a unified view of the design, using integrated tools and flows. It also requires that DFT tools have zero impact on critically important timing closure flows.

The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

Summary form only given. The last 25 years has seen a dramatic increase in gate count and the Design for Testability techniques such as Full Scan, LSSD, BIST, etc. have been developed to cope with this. However, there is now a significant difference brought on by the technology developments facing us. The onset of deep sub-micron (now currently alluded to as Nanometer Technology) is changing the way chips are being designed and manufactured. Because of the large capacity of these new chips, plus the expense of new designs, embedded systems are setting the pace for today and the future. New problems are arising that are driving design automation to integrate all the tools that are needed to successfully take a design from concept to reality in this new design environment. Test is one part of this process that is getting significant attention. An area once classified as a "back end" process in the design flow is moving closer to the "front end". Design methodologies are incorporating test-related structures in the beginning of the design cycle. In addition, standards to manage the test complexity of these large designs are being proposed. For example, IEEE P1500 is working towards defining a structure for embedded cores such that tests can be delivered to these cores. This alone is a strong challenge for the Test Community. It is clear that the design and testing of embedded systems is the key challenge facing the Test Community.

The onset of deep sub-micron (now currently alluded to as nanometer technology) is changing the way chips are being designed and manufactured. New problems are arising that are driving design automation to integrate all the tools that are needed to successfully take a design from concept to reality. Test is one part of this process that is getting significant attention. An area once classified as a "back end" process in the design flow is moving closer to the "front end". Design methodologies are incorporating test-related structures in the beginning of the design cycle. Manufacturability of the complex designs caused by the excess silicon available is a significant issue. With these nanometer technologies comes a number of issues which the SIA Roadmap refers to as Grand Challenges. These include >1 GHz cycle time, higher sensitivity to crosstalk, and tester costs. This paper will examine the challenges that face testing in this new frontier.

The traditional goal of an ATPG algorithm is to achieve a high fault coverage by producing a small number of tests. However, since usually a high fault coverage does not imply a high defect coverage, such an objective can mislead us to overtrust an ATPG method which is optimal for faults but inefficient for defects. The paper presents several new principles to design an ATPG algorithm for solve this problem. The new principles direct an ATPG algorithm to improve its efficiency and reliability for detecting the non target defects through the target faults. Theory and experiments are presented to demonstrate the superiority of the new principles and the new test generation algorithm.

The traditional ATPG method relies upon faults to target all defects. Since faults do not model all possible defects, testing quality depends on the fortuitous detection of non-target defects. By analyzing different ATPG approaches, this paper intends to identify critical factors that may greatly affect the fortuitous detection. For enhancing the fortuitous detection of non-target defects through target faults, new concepts and novel ATPG methods are proposed.

While technology is changing the face of the world, it itself is changing by leaps and bounds; there is a continuing trend to put more functionality on the same piece of silicon. Without major changes in the CMOS technology, it has been shown that the scaling of devices has significant impact on the effectiveness of Iddq testing. The sensitivity of Iddq testing to individual device parameters is studied. It is explained how Iddq testing becomes increasingly ineffective in the scaled product with respect to most parameters and can be improved with others.

This paper describes a weight generation algorithm that is driven by tests created by a test generator. New concepts with regard to throwing away ineffective weight sets are developed as an integral part of the system. Various parameters that help improve the effectiveness of the weight generation system are discussed.

The purpose of this paper is to present a methodology for the evaluation of the Defect Level in an IC design environment. The methodology is based on the extension of Williams-Brown formula to nonequiprobable faults, which are collected from the IC layout, using the information on a typical IC process line defect statistics. The concept of weighted fault coverage is introduced, and the Defect Level (DL) evaluated for the Poisson and the negative binomial yield models. It is shown that DL depends on the critical areas associated with undetected faults, and their correspondent defect densities. Simulation results are presented, which highlight that the classic single Line Stuck-At (LSA) fault coverage is a unreliable metric of test quality. Moreover, results show that the efficiency of a given set of test patterns strongly depends on the physical design and defect statistics.

How can we guarantee that a testing method will stably and efficiently achieve a very low defective part level? Traditional testing methods rely upon faults to model all defects. As technology advances, this approach becomes increasingly questionable. If only a subset of defects are modeled as faults, then as fault coverage approaches 100%, the tests mill be more and more biased in favor of fault detection. Unfortunately, this reduces the testing efficiency for defects and limits the quality level that we can achieve. In this paper, we propose models for the testing process and suggest a solution which we call "unbiased test generation". We define two types of testing bias, and these new metrics can be used to compare and evaluate test generation methods in practice.

Testing is an indispensable process to weed out the defective parts coming out of the manufacturing process. Traditionally, test generation targets on a specific fault model, usually the single stuck-at fault model, to produce tests that are expected to identify defects such as unintended shorts and opens. With this approach, the test quality relies on fortuitous detection of the non-target defects. As the quality demands and circuit sizes increase, the feasibility of test generation on a single fault model becomes questionable. In the paper, we present empirical data from experiments on ISCAS benchmark circuits to demonstrate that using traditional methods the probability of detecting nontarget defects drops rapidly as the fault coverage approaches 100%. By assuming surrogates, we explain the mechanism which produces this effect and describe a new test pattern generation approach with better testing efficiency.

This paper describes the design of an efficient weighted random pattern system. The performance of the system is measured by the number of weight sets and the number of weighted random patterns required for high fault coverage. Various heuristics that affect the performance of the system are discussed and an experimental evaluation is provided.

The stuck-at fault model has been used over decades as a guide to the test generation process and as an evaluation mechanism for the quality of the test set. As demands on quality have increased, the use of the stuck-at fault model as a predictor of the defect level has been questioned. This paper provides some insight on the issue and shows the limitations of using the stuck-at fault coverage to predict the defect level. The authors demonstrate that as defect level decreases the uncertainty of the estimate grows.>

Delay testing at the operational system clock rate can detect system timing failures caused by delay faults. However, delay fault coverage in terms of the percentage of the number of tested faults may not be an effective measure of delay testing. A quantitative delay fault coverage model to provide a figure of merit for delay testing is presented. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A new statistical delay fault coverage model is established. A defect level model is also proposed as a function of the yield of a manufacturing process and the new statistical delay fault coverage. A new delay testing strategy driven by the defect level for delay faults is proposed.>

As CAD tools become more sophisticated, they can synthesize logic netivorks that more nearly optimize the circuit area resources to maximize operating speeds.In this work we show, through formal arguments, that the path delays in such optimized networks will follow a more compact distribution and, in the extreme in some networks, will all be equal to the m"mum delay through the network (cycle time).The impact of this type of synthesized network on delay testing will be shown and compared to the case for nonoptim"zed designs.Finally, recommendations will be made on how network tim"ng optimization can be abne in such a way as to minimize the adverse impact on product yield.

As electronic CAD synthesis tools become more powerful, they will increasingly refine delay measiirements and adjust path delays so as to increase the clock rate or to reduce the chip area. This paper discusses the implications of such events on testing for delay defects. We provide a timing optimization procedure and show that the resultant density function of path delays is a delta function. Finally, we discuss the impact of timing optimization on the yield of a manufacturing process and the defect level for delay faults.

Board test using functioiial self-test code can be augmented by concurrently sampling signals at chip boundaries, compressing this data, and verifying its signature in-line in the code. This is a general method to enhance board test and diagnosis, po1,erXtidy adding every chip J/O pin as an observation point that is observed frequently and coupled to the self-test. Tests continue to execute at the normal board operating speed. This combination of fnnctional and strudural testing offers improved effectiveness over functional testing alone.

An algorithm, ALG-MK, for computing exact aliasing probabilities in signature analysis is derived from a Markov process model of signature analysis. A previous algorithm, ALG-BL, which was derived from a Boolean expressions formulation of the problem, is reformulated so that it can also be reviewed as being based on a Markov process. Both algorithms compute exact aliasing probabilities in signature analysis. The computational complexities of the two models are compared. It is shown that the time complexity of the iterative algorithm ALG-MK is O(L2/sup k/), disregarding slight possible start-up and termination improvements, while that of ALG-BL is O(Lf2/sup k+f/), where k is the size of the signature register, f is the number of feedback taps, and L is the test sequence length. ALG-BL requires more shift and add operations, but requires half the number of floating-point multiplications that ALG-MK requires. The space complexity of ALG-MK is O(2/sup k/), while that of ALG-BL is O(2/sup k+f/). It is also shown that ALG-MK and ALG-BL are formally related through a linear transformation of their state vectors. Both algorithms may be used to study aliasing under generalized error models.>

A quantitative delay fault coverage model is discussed to provide a figure of merit for delay testing. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A statistical delay fault coverage model is established. A defect-level model is also proposed as a function of the yield of a manufacturing process and the statistical delay fault coverage.>

A starting point for a set of design for testability (DFT) principles that can be used with mixed signal integrated circuits is presented. The authors argue that an effective DFT technique should enhance the ability to perform digital signal processing and other modern test techniques on analog macros embedded in the integrated circuit, since quality will be a driving force with increasing integration. The proposed test methodology consists of (1) establishing the digital test model for testing of digital logic and (2) establishing the analog test mode and each of the submodes (called test configurations) for serial or parallel testing of analog partitions. Digital and analog circuitry must be isolated from each other, i.e. an uncontrolled analog signal must not be able to affect the digital test mode and vice versa.>

The testability by random test patterns of faults in the logic surrounding embedded RAMs is studied. Upper and lower bounds on the probability that a fault is caught are obtained by analyzing a modified, purely combinational circuit without the RAM. This analysis can be done with standard testability analysis techniques. The analysis is applied to an embedded two-port RAM.>

Aliasing errors in linear feedback shift registers (LFSRs) used as signature analysis registers in self-testing networks are considered. A bound on aliasing is established by a straightforward algebraic analysis of LFSRs. It is calculated as a function of p, the probability of an error occurring at an output of the network under test. This bound is robust but is only good for p close to 1/2. To investigate the question of what happens to aliasing errors in general, the function of LFSRs is modeled by a Markov process and a solution is obtained by the z-transform. It is shown that for p>1/2 the aliasing probability for primitive polynomials converges much faster to the final steady-state value than for nonprimitive polynomials. For values of p>

This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon appear in new designs.

There is a continuing increase in the use of correlation in engineering. In these applications some or all of the signals to be analyzed may be obscured by noise. Since determination of the autocorrelation or cross correlation requires knowledge of the signals for all time, one must use the observed signals to obtain an estimate of the desired correlation function. These estimates, autocorrelograms or crosscorrelograms, are affected when the signal is obscured by noise. A theoretical investigation of the noise-induced error in correlograms is presented. It is shown that the rms error is inversely proportional to the square root of the record length for virtually any noise which might be encountered. This provides a guide for the reduction of the noise error to any desired level. In addition, bounds on the error are determined for some more common types of noise. Experimental results are described which verify the theoretical developments. The theoretical results are applied to a study of the transmission of action potentials through the cockroach ganglion.