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Laura Effinger-Dean

dblp:11/4409 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2 · 2 first-authorSystems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Concurrent programming · 79% Program analysis · 21%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 44% Memory systems · 44% Hardware reliability and fault tolerance · 13%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming › concurrency bug detection
data race detection
0.112012
IFRit: interference-free regions for dynamic data-race detection · OOPSLA 2012
Program analysis
dynamic analysis
0.112012
IFRit: interference-free regions for dynamic data-race detection · OOPSLA 2012
Concurrent programming › concurrency bug detection › data race detection
dynamic race detection
0.112012
IFRit: interference-free regions for dynamic data-race detection · OOPSLA 2012
Concurrent programming
concurrency bugs
0.112011
The impact of memory models on software reliability in multiprocessors · PODC 2011
Concurrent programming › concurrency bugs
thread interleaving
0.112011
The impact of memory models on software reliability in multiprocessors · PODC 2011
Memory systems › memory consistency
memory consistency model
0.112011
The impact of memory models on software reliability in multiprocessors · PODC 2011
Parallel and multicore computing
memory model
0.112011
The impact of memory models on software reliability in multiprocessors · PODC 2011
Hardware reliability and fault tolerance › system reliability
software reliability
0.012011
The impact of memory models on software reliability in multiprocessors · PODC 2011

Methods — techniques the papers use, named apart from their topics

vulnerability bound · 0.2probabilistic model · 0.2happens-before analysis · 0.1compile-time instrumentation · 0.1
YearPublicationVenuePosition
2012 IFRit: interference-free regions for dynamic data-race detection
abstract
We propose a new algorithm for dynamic data-race detection. Our algorithm reports no false positives and runs on arbitrary C and C++ code. Unlike previous algorithms, we do not have to instrument every memory access or track a full happens-before relation. Our data-race detector, which we call IFRit, is based on a run-time abstraction called an interference-free region (IFR). An IFR is an interval of one thread's execution during which any write to a specific variable by a different thread is a data race. We insert instrumentation at compile time to monitor active IFRs at run-time. If the runtime observes overlapping IFRs for conflicting accesses to the same variable in two different threads, it reports a race. The static analysis aggregates information for multiple accesses to the same variable, avoiding the expense of having to instrument every memory access in the program.
Laura Effinger-Dean, Brandon Lucia, Luis Ceze, Dan Grossman, Hans-Juergen Boehm
OOPSLA1
2011 The impact of memory models on software reliability in multiprocessors
abstract
The memory consistency model is a fundamental system property characterizing a multiprocessor. The relative merits of strict versus relaxed memory models have been widely debated in terms of their impact on performance, hardware complexity and programmability. This paper adds a new dimension to this discussion: the impact of memory models on software reliability. By allowing some instructions to reorder, weak memory models may expand the window between critical memory operations. This can increase the chance of an undesirable thread-interleaving, thus allowing an otherwise-unlikely concurrency bug to manifest. To explore this phenomenon, we define and study a probabilistic model of shared-memory parallel programs that takes into account such reordering. We use this model to formally derive bounds on the vulnerability to concurrency bugs of different memory models. Our results show that for 2 concurrent threads, weaker memory models do indeed have a higher likelihood of allowing bugs. On the other hand, we show that as the number of parallel, buggy threads increases, the gap between the different memory models becomes proportionally insignificant, and thus the importance of using a strict memory model diminishes.
Alexander Jaffe, Thomas Moscibroda, Laura Effinger-Dean, Luis Ceze, Karin Strauss
PODC3
2008 Transactional events for ML
abstract
Transactional events (TE) are an approach to concurrent programming that enriches the first-class synchronous message-passing of Concurrent ML (CML) with a combinator that allows multiple messages to be passed as part of one all-or-nothing synchronization. Donnelly and Fluet (2006) designed and implemented TE as a Haskell library and demonstrated that it enables elegant solutions to programming patterns that are awkward or impossible in CML. However, both the definition and the implementation of TE relied fundamentally on the code in a synchronization not using mutable memory, an unreasonable assumption for mostly functional languages like ML where functional interfaces may have impure implementations.
Laura Effinger-Dean, Matthew Kehrt, Dan Grossman
ICFP1