We present a voltage-controlled oscillator (VCO)-based electron paramagnetic resonance (EPR) sensor featuring an enhanced sensing area for a high concentration sensitivity and improved homogeneity compared to conventional, chip-integrated planar sensors. Prior designs have relied on VCO-array configurations to expand the sensing area, which comes at the cost of increased power consumption. Here, the relatively small diameters of the individual coil elements limit the homogeneous region in the direction perpendicular to the chip surface. To address these limitations, we propose the use of inductance-capacitance (LC) VCO-based EPR detectors with large coil diameters with a laser-fabricated hole to create a large sensitive volume with high homogeneity of the microwave B1field inside the coil. Despite the enlarged coil diameter and the correspondingly large inductance, the VCO-based detector achieves a low phase noise (PN) of -116 dBc/Hz at a 1 MHz offset from a center frequency of 6.75 GHz, and a 10 % frequency tuning range. The presented sensor frontend incorporates the VCO-based EPR detector inside an integer-N phase-locked loop (PLL), enabling precise phase and frequency control from an external low-frequency reference. The C-band operation of the presented VCO-based EPR detector is compatible with the static magnetic fields achievable with compact permanent magnets. The proposed sensor is electrically characterized and validated in the target EPR application using standard EPR samples of BDPA (α, γ-bisdiphenylene-β-phenylallyl) and TEM-POL (2,2,6,6-tetramethyl-4-hydroxy-piperidine-1-oxyl), achieving a spin sensitivity of 5 × 109spins/(G Hz1/2) and concentration sensitivity of 15.6 µM/(G Hz1/2), respectively.

This paper presents a 16-channel sensor ASIC for a biomedical implant for the monitoring of pancreatic beta-cell activity and the detection of the fraction of plateau phase (FOPP). The aim is to better understand type 2 diabetes mellitus with the goal of developing new therapies. To achieve this, the ASIC presents a unique solution by combining low-power and long-term monitoring with high-precision measurement of the electrical activity of the beta-cells. In the direct readout mode, the entire signal is captured using the on-chip 10-bit analog-to-digital converter. In the FOPP mode, a simple yet effective detection scheme using signal comparators is presented. The chip was designed and fabricated in the XFAB XH035 CMOS technology. Experimental results validate the concept and show good operation for all 16 channels over a range of frequencies between 1 Hz to 1 kHz.

The excellent performance of quantum magnetometers based on nitrogen-vacancy (NV) centers in diamond, including their high sensitivity, their wide dynamic range, and the possibility for a calibration-free operation, renders them a very promising alternative to classical magnetic field sensors. However, existing lab prototypes of NV center sensors still suffer from a large volume and non-scalable manufacturing technologies. To mitigate this problem, in this paper, we present a miniaturized and scalable microwave electronics platform for quantum magnetometry based on an S-band SiGe BiCMOS transmitter (TX) chip and a custom-designed resonator manufactured on a microwave printed circuit board. The fabricated TX chip can deliver a high saturated output power of 19dBm at a center frequency of 2.87GHz over a wide relative bandwidth of 38.3% of the center frequency to a 50Ω load while occupying a compact die area of 0.593mm2. To manipulate the spin state of NV centers efficiently, we use two of the presented TX chips to drive a newly proposed differential resonator, which provides microwave magnetic fields of B1=179μT over a large active area of 18.48×104μm2. Continuous-wave and pulsed optically detected magnetic resonance (ODMR) measurements are used to verify the excellent performance of the proposed platform compared to the state-of-the-art. In these experiments, the presented platform produced Rabi frequencies up to 5.81MHz.

In this paper, we present a miniaturized chip-based Overhauser dynamic nuclear polarization (ODNP) platform for enhancing detection sensitivity and, thereby, improving the achievable limit of detection. The presented system uses three custom-designed ASICs for the excitation and the detection of the NMR signal as well as the generation and preamplification of the required microwave (MW) signal. A commercial baredie GaN power amplifier is used in addition to achieve the driving strength of up to 26 dBm at 7 GHz required for the target ODNP application. Moreover, the wide bandwidth of the custom-designed, printed MW Alderman-Grant (AG) resonator allows for an indirect measurement of the electron spin resonance (ESR) signal of the utilized DNP agent without the need for an additional ESR spectrometer. Overall, the presented system achieves an ODNP enhancement factor of 50 with an active volume of 500 nL, the latter number improving the state-of-the-art in chip-based ODNP platforms by a factor of 500×.

Test application to state-of-the-art integrated circuits usually consists of multiple test insertions: wafer sort, final test and system-level test (SLT). This paper considers optimization of test content, taking requirements of specific scenarios, such as expected yield levels, test costs and criticality of test escapes, into account. An integrated cost model is proposed and applied to four different test setups on a medium-complexity RISC-V microprocessor. Our results indicate opportunities for up to ~ 40% total cost reduction compared to today’s industrial practice. They also provide insights on the relative importance of various cost contributors, such as the number of available scan test insertions or the specific SLT workload used.

With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects. This survey provides an overview of recent developments in this quickly-evolving field. We start with discussing the application of state-of-the-art functional and system-level test solutions to RISC-V processors. Then, we discuss the use of RISC-V processors for safety-related applications; to this end, we outline the essential techniques necessary to obtain safety both in the functional and in the timing domain and review recent processor designs with safety features. Finally, we survey the different aspects of security with respect to RISC-V implementations and discuss the relationship between cryptographic protocols and primitives on the one hand and the RISC-V processor architecture and hardware implementation on the other. We also comment on the role of a RISC-V processor for system security and its resilience against side-channel attacks.

In this paper, we present a broadband (5-780MHz) transceiver ASIC optimized for$^{ \boldsymbol {1}}\text{H}$and X-nuclei nuclear magnetic resonance (NMR) with external custom-designed microcoils. The NMR-on-a-chip transceiver is realized in a 0.13$\mu \text{m}$BiCMOS technology, consumes an area of$1100 \boldsymbol {\times }900\mu \text{m}\,\,\boldsymbol {^{2}}$, and integrates a quadrature receiver, consisting of a low-noise amplifier, a quadrature downconversion mixer, and intermediate-frequency variable gain amplifiers, a power amplifier, and a frequency synthesizer on a single chip. An extensive noise analysis of the BJT-based low-noise amplifier with regard to the optimum source impedance provides simplified expressions for an optimized LNA design for broadband NMR-on-a-chip applications. The NMR-on-chip transceiver provides a measured state-of-the-art input-referred voltage noise of 610pV/$\sqrt {\text {Hz}}$and a maximum RX gain of 66dB. In combination with an external, custom-designed solenoidal microcoil, the presented NMR-on-a-chip transceiver achieves a state-of-the-art normalized$^{ \boldsymbol {1}}\text{H}$spin sensitivity of$7.2 \boldsymbol {\times } 10^{ \boldsymbol {17}}$spins$/\sqrt {\text {Hz}}\cdot \text {T}^{ \boldsymbol {2}}/\text{m}$with an untuned, i.e. broadband front-end. Proof of concept NMR experiments on multiple nuclei ($^{ \boldsymbol {1}}\text{H}$,$^{ \boldsymbol {2}}\text{H}$,$^{ \boldsymbol {13}}\text{C}$, and$^{ \boldsymbol {19}}\text{F}$) verify the applicability of the proposed untuned, broadband approach.

Test methods that can keep up with the ongoing increase in complexity of semiconductor products and their underlying technologies are an essential prerequisite for maintaining quality and safety of our daily lives and for continued success of our economies and societies. There is a huge potential how test methods can benefit from recent breakthroughs in domains such as artificial intelligence, data analytics, virtual/augmented reality, and security. The Graduate School on “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR) at the University of Stuttgart is a large-scale, radically interdisciplinary effort to address the scientific-technological challenges in this domain. It is funded by Advantest, one of the world leaders in automatic test equipment. In this paper, we describe the overall philosophy of the Graduate School and the specific scientific questions targeted by its ten projects.

In this paper, we present a continuous-time current-mode $\Sigma\triangle$ modulator (CT C-SDM) with finite impulse response (FIR) feedback to increase clock jitter robustness while preserving the anti-aliasing filtering (AAF) property of a CT modulator. The modulator also features a newly proposed DC servo loop (DSL) that extends the modulator’s dynamic range in applications with a large DC bias current. This improvement breaks the intrinsic tradeoff between dynamic range and quantization noise floor of C-SDM for applications which require the digitization of AC currents in the presence of strong DC bias currents. The proposed modulator architecture has been manufactured in 180nm CMOS, and consumes 64mW from a 3. 3V supply. The chip’s measured peak SNR and SNDR are 77 dB and 76.8 dB, respectively. The modulator can accommodate AC signal currents up to 137$\mu \mathrm{A}_{\mathrm{p}\mathrm{p}}$ and features an integrated noise of 6.9 n$\mathrm{A}_{\mathrm{r}\mathrm{m}\mathrm{s}}$ over a 200 kHz bandwidth, corresponding to a noise floor of 15 pA/$\sqrt{\mathrm{H}\mathrm{z}}$. An off-chip implementation of the proposed DSL verifies its positive effect on the modulator’s dynamic range (DR) without deteriorating the modulator’s noise performance and/or stability properties.

In this paper, we present an integrator-differentiator transimpedance amplifier (I-D-TIA) with a dc compensation, which incorporates widely tunable multi-element pseudo-resistors (MEPRs) in its dc servo loop and ac signal path. The implemented MEPR in the dc path is continuously tunable from$460 \,\mathrm {k\Omega }$to$300 \,\mathrm {G\Omega }$allowing the TIA to process dc currents with a dynamic range of more than$100 \,\mathrm {dB}$. The MEPR in the differentiator ac signal path provides a tunable resistance between$0.3 \,\mathrm {M\Omega }$and$100 \,\mathrm {M\Omega }$, resulting in an overall ac transimpedance between$3 \,\mathrm {M\Omega }$and$1 \,\mathrm {G\Omega }$. For the lowest ac transimpedance, a bandwidth of$10 \,\mathrm {MHz}$is achieved. The TIA provides a minimum input-referred current noise density of$1.6\,\mathrm {fA}/\mathrm {\sqrt {Hz}}$. The implemented MEPR has been optimized regarding its high-frequency noise by minimizing its parasitic capacitances. The MEPR shows an inherent shot noise suppression such that its noise stays close to the theoretical thermal noise limit and significantly below the theoretical shot noise limit, even for large dc currents. By using a sub-VSS supply for the MEPR, the asymmetry in its output characteristic is greatly reduced, leading to a linear signal swing of$1.5\,\mathrm {V_{pp}}$with a THD below$1 \mathrm {\%}$on a$1.8-\mathrm {V}$supply. Thanks to this high linearity, large bandwidth, and high dc current dynamic range, the proposed TIA can be used in a wide variety of applications from high-sensitivity, low-bandwidth lock-in detection to transient current sensing with sub-microsecond timing resolutions.

RISC-V has emerged as a viable solution on academia and industry. However, to use open source hardware for safety-critical applications, we need a deep understanding of the way in which well established mechanisms for testing and reliability could be integrated and deployed on the RISC-V ecosystem, and we need a clear knowledge on how such an ecosystem can be leveraged to improve security. This paper includes four contributions presenting the potential of RISC-V in security research, the way in which RISC-V can be hardened against power analysis attacks, how to implement, using RISC-V, software and hardware/software solutions for dual core lock step, and how to perform system-level testing in the RISC-V ecosystem.

System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.

In this paper, we present a fully integrated transceiver ASIC for low field NMR spectroscopy. The chip integrates a conventional low intermediate frequency (low-IF) receiver together with a high-voltage (HV) H-bridge power amplifier (PA) and a PLL frequency synthesizer. The receiver consists of a low noise amplifier (LNA), a quadrature down-conversion mixer and a baseband amplifier. It achieves a measured input-referred voltage noise density of 1.1 nV/√Hz;. The integrated PLL frequency synthesizer supports operating frequencies between 4 MHz and 100 MHz, covering all relevant Larmor frequencies of benchtop and portable NMR. The on-chip PA can drive up to 1.4 Appinto a 1Ω resistor and 1.6 Appinto a 3mm, parallel-tuned NMR coil. When operating with a 3mm NMR coil inside a 1.45T unshimmed NMR magnet, the system achieves a spin sensitivity of 9.2 × 1015spins/√Hz and a concentration sensitivity of 1.79 mM/√Hz.

In this paper, we present a mixed-logic dynamical (MLD) system model that allows for an iron-clad prediction of the stability of Incremental Sigma Delta (I-ΣΔ) modulators. The model extends the mixed logic dynamical description of freely-running Sigma-Delta (ΣΔ) modulators with single-bit quantizers presented in [1] to the multibit case. Moreover, we use the derived model to compare I-ΣΔs with different loop filter orders and different number of quantizer levels concerning their stability.

In this paper, we present a CMOS-based miniaturized magnetic resonance (MR) system for magnetic field and trajectory mapping incorporating an electromagnetic interference (EMI) robust optical link. The system consists of a custom-designed, CMOS-based active NMR field probe, a custom-designed, single-bit ΣΔ modulator and a commercial optical link. The low-IF architecture of the transceiver ASIC, reduces the required bandwidth in the digitizer to a few hundred kilohertz, enabling the use of a single-bit ΣΔ modulator, whose high frequency, one bit data stream is ideally suited for feeding the following optical link. The custom ΣΔ modulator uses a third order loop filter and employs a 12-tap FIR DAC to increase its robustness against clock jitter. It is manufactured in a 0.18 μm CMOS technology and achieves an SNDR of 72.19 dB over a Nyquist bandwidth of 800 kHz. In the proposed setup, the 1-bit output stream of the ΣΔ modulator directly feeds the driver of a commercial optical fiber link to transmit the NMR data from inside the NMR magnet to the remotely located digital signal processing unit with a very high robustness against EMI. In-situ NMR experiments with a 1.45 T benchtop magnet using a silicone sample demonstrate the very good performance of the overall system, achieving a frequency resolution of 12.6 Hz or 200 ppb in the estimation of the sample's NMR resonance frequency. This corresponds to an effective magnetic field resolution of 290 nT.

Ultrashort echo time imaging on clinical systems is still limited by the rather long radio frequency switching times achievable with standard front end concepts. In this contribution, an independent parallel receive-only system is interfaced to an unmodified clinical MRI system, enabling imaging of species with ultrashort relaxation times, such as bone, tendon, teeth, or lung tissue. Synchronization of the system is achieved by an electronically decoupled one-way trigger line, a clock reference signal, and RF pulse tracking, thus ensuring minimal interference with the host system. With the proposed system, an acquisition delay of 3 μs is experimentally demonstrated.

In this paper, we present a new architecture for the receive-chain in clinical X-nuclei magnetic resonance imaging (MRI) experiments. The proposed architecture requires only a single tuning capacitor to tune the MRI receive coil to the Larmor frequency of the nucleus of interest. The tuning capacitor provides a noise-free preamplification of the MR signal, allowing for relaxed noise constraints in the design of the following high impedance low noise amplifier (LNA). Together with the new architecture, we present a custom designed CMOS LNA with a passband between 1.5 MHz and 90 MHz, covering all clinically relevant nuclei in a 1.5 T MRI system. The custom designed LNA comprises two amplification stages providing a measured total gain of 44 dB and an on-chip DC servo loop to mitigate the effect of offsets in the presence of the large on-chip DC gain. The DC servo loop introduces a measured lower passband frequency at 1.5 MHz. The LNA displays a measured low input referred voltage noise spectral density of 200 pV/√Hz. X-nuclei MRI experiments performed on proton and fluor samples demonstrate the excellent performance of the proposed architecture and LNA implementation.

In this paper, we present a new strategy for energy-efficient and noise-aware LC tank oscillator design. In contrast to commonly used design concepts, the proposed method fully accounts for the oscillator nonlinearity. To this end, the proposed approach uses a perturbation theory based approach to obtain nonlinear estimates of both the oscillation amplitude and the oscillation frequency. Then, to model the oscillator phase noise, a variant of the stochastic averaging method initially proposed by Stratonovich is used to obtain an analytical model of the oscillator phase and frequency noise in the white noise regime. From these analytical expressions, we identify the oscillator bias current and coil inductance as important design parameters and show how a single 3D-phase noise plot can be used to obtain a very good starting point for a final oscillator optimization using numerical simulations. Finally, the proposed method is validated using an example design in a 130 nm CMOS technology.

In this paper, a comparison between three different current readouts for micro-potentiostats is presented: resistive transimpedance amplifier (R-TIA), capacitive transimpedance amplifier (C-TIA), and current-mode continuous-time sigma-delta modulator (Current-CTSDM). The comparison is carried out on the signal transfer function, the required amplifier gain-bandwidth (GBW), its input referred noise current, required area and power, and dynamic range. Each approach and its limitations are separately discussed. The three systems have been simulated using VerilogA models and the results are compared. It is shown that each system comes with its own limitations, however current-mode CTSDM are more beneficial due to their intrinsic digitization.

Developing custom-built MR coils is a cumbersome task, in which an a priori prediction of the coils' SNR performance, their sensitivity pattern, and their depth of penetration helps to greatly speed up the design process by reducing the required hardware manufacturing iterations. The simulation-based design flow presented in this paper takes the entire MR imaging process into account. That is, it includes all geometric and material properties of the coil and the phantom, the thermal noise as well as the target MR sequences. The proposed simulation-driven design flow is validated using a manufactured prototype coil, whose performance was optimized regarding its SNR performance, based on the presented design flow, by comparing the coil's measured performance against the simulated results. In these experiments, the mean and the standard deviation of the relative error between the simulated and measured coil sensitivity pattern were found to be and . Moreover, the peak deviation between the simulated and measured voxel SNR was found to be less than 4%, indicating that simulations are in good accordance with the measured results, validating the proposed software-based design approach.

Clock jitter sensitivity is a well-known drawback of continuous-time ΣΔ modulators. Although there exist various methods to alleviate the jitter influence, most are only effective in reducing noise incurred by out-of-band quantization noise. However, due to the steadily increasing signal frequency in receiver applications, the dominant jitter influence rather originates from the mixing between the close to in-band interferers and the close-in clock phase noise, either in a mixer or in the DAC of a bandpass ΣΔ modulator. This mixing results in additional in-band noise which cannot be reduced by existing solutions. In this paper, we use a reconfigurable digital filtering method for close to in-band interferer suppression in bandpass ΣΔ modulators, and demonstrate its effectiveness in improving phase noise tolerance through simulation. Additionally, a technique to simplify the implementation of the digital filters is proposed.

In this paper, we discuss the requirements for an NMR setup to allow for combined NMR microscopy and spectroscopy using planar microcoils to study metabolic processes in vivo. Here, NMR is particularly suitable because — unlike most other currently used methods — it can deliver structural information as well as qualitative and quantitative information about the molecules involved in cellular processes. More specifically, based on the reciprocity principle, we derive why previously presented fully-integrated CMOS receivers using on-chip NMR coils in receive-only mode are not suitable for in-vivo spectroscopy applications. As a solution to this problem, we propose the use of fully-integrated transceivers which use their on-chip planar microcoils in TX/RX mode as an ideal tool for combined in-vivo NMR imaging and spectroscopy. Measurements using a planar coil on a thin silicon substrate validate the theoretical analysis.

Together with the increasingly demanding DAC, the design of the comparator introduces a big challenge for the implementation of high resolution SAR ADCs. Therefore, several state of the art works investigated improved comparator architectures aiming for higher resolution. However, those architectures in most cases resulted either in excessive power consumption or compromised conversion speed. For improved performance and power efficiency this paper proposes the use of two dynamic comparators in a 14-bit SAR ADC. The first coarse decisions are made by a low power comparator, while the second comparator applies an automatic noise reduction technique to perform accurate decisions around the LSB. The proposal includes SAR conversion which applies two switching schemes a monotonic and a differential one. The design is partially implemented and simulated on transistor level using a 40 nm CMOS technology. The ADC is operated with a sampling frequency of 1.6 MS/s and features an SNDR above 81 dB and an SFDR above 97 dB. The estimated power consumption of the two comparators is 44 μW and about 27 μW for the DAC reference.

Fast and high-resolution scanning ion-conductance microscopy (SICM) experiments require a high speed, low noise and low distortion transimpedance amplifier (TIA) as interface circuit. Recent high performance TIAs utilize capacitive feedback. However, their inability to treat DC currents renders them unfavorable for SICM applications and resistive TIAs remain the best choice here. To address this problem, this paper presents an active MOS resistor with improved robustness and linearity to make it suitable for its use as feedback resistor in TIAs for SICM experiments. The presented device features PMOS transistors operating in weak inversion as pseudo-resistors to obtain reduced noise compared to ohmic resistors of the same value. A novel bias circuit is introduced which compensates process variations of the pseudo-resistor. Monte Carlo simulation shows a standard deviation of 3.6 % of the overall resistance. The connection of multiple pseudo-resistors in series, while preserving equal overall resistance, linearizes the I-V characteristic and decreases the total harmonic distortion to 0.26 %. The presented device is incorporated into a low noise and high speed TIA achieving a simulated SNDR of 49 dB over a bandwidth of 1 MHz enabling fast high-resolution topography imaging using SICM.

This paper presents a fully integrated, bidirectional, neural interface, which is composed of a high voltage (HV) stimulator and a low voltage (LV) neural front-end with active, spectral separation. The stimulator uses a supply of ±9V in order to achieve a high voltage compliance (VC), whereas the recorder has a supply voltage of 3 V for high power efficiency. By using a HV transistor to separate the two parts, a safe operation of stimulator and recorder with different supply voltages can be guaranteed. Thereby the presented architecture can deliver a maximum stimulation current of ±10mA with a dynamic range of 50 dB and a VC of ±8.2 V. The implemented recording part consumes 52 μW and achieves a simulated input referred noise of 2.5μVrms in the low frequency band from 0.1 Hz to 200 Hz and 3.1 μVrms in the high frequency band from 200 Hz to 7.5 kHz. The combined recorder/stimulator requires 0.378 mm2 per channel. A prototype of the interface has been implemented and manufactured in a standard 0.18 μm HV CMOS technology.

We report on an experimental low power transcutaneous optical telemetric link (TOTL) for high speed biomedical data transfer. By decreasing the bandwidth to data rate ratio, a silicon photodiode with large active size can be used to significantly increase transmission efficiency as well as misalignment tolerance. Additionally, a custom-designed transimpedance amplifier (TIA) with low input referred noise and a modified on-off keying with a custom designed low power VCSEL (vertical cavity surface emitting laser) driver are used to further reduce the required power consumption. The proposed system transmits data up to 75 Mbps through 6 mm thick tissue, in the presence of a 4 mm misalignment while achieving a BER better than 10−5, with a power consumption lower than 2.8 mW.

In this work, an unscented Kalman filter with improved numerical properties is shown to be able to simultaneously estimate the major nonidealities of continuous-time sigma-delta modulators. Circuit imperfections in sigma-delta modulators like, e.g., nonlinearities in the feedback digital-to-analog converters are known to highly reduce the modulators's performance. The state of the art shows several techniques to compensate for some of these nonidealities, whereby most of the methods only focus on single parameters or can only be applied to specific modulator structures. The presented method is capable of estimating the most serious nonideal circuit parameters concurrently whilst not being limited to specific modulator structures.

We present in this paper the design of a wide-band efficiency-enhanced CMOS rectifier. A novel semi-active diode is proposed to minimize both the diode forward voltage drop and the reverse leakage current. This is achieved by dynamically configuring the rectification device as a threshold compensated diode in the on-state while a standard MOS diode in the offstate, respectively. The proposed rectifier is implemented in a 0.35μm 4M/2P standard CMOS process. In simulation, with 5.5V AC input at 13.56MHz, the rectifier outputs 4.94V DC voltage across a 1.2kΩ load resistor, achieving 87% power conversion efficiency (PCE) and 90% voltage conversion efficiency (VCE). The PCE and VCE can be maintained from 1MHz to 20MHz input frequency, with only 3% deviation in the PCE and 2% deviation in the VCE. In addition, the performance of the rectifier is self-compensated over temperature and process. From -40°C to +130°C, the simulated VCE varies within 2% from 89.6% to 87.7%, while the PCE stays almost constant at 86%. With 200 Monte Carlo samples, the standard deviation in the PCE and VCE are as low as 0.56% and 0.57%, respectively.

This paper shows a neural stimulator with 15V supply voltage combined with a neural low-noise amplifier (LNA) with a supply of ±1.65V around the common mode voltage (VCM) of 7.5V. In most implementations, the stimulator and recorder use the same supply domain, thus either leading to low voltage compliance (VC) for the stimulator or to high power consumption in the recorder. Obviously, a separation of both is the preferable choice, but comes with the challenge of effective protection of the low voltage (LV) sensitive input nodes of the recorder. A high voltage (HV) transistor used as a switch between the two parts enables different supply voltages for stimulator and recorder. Thus, a high current stimulator with high VC can be combined with a high efficient LV neural recorder. The presented implementation shows a stimulator with a maximum stimulation current of ±15mA with 5-bit resolution out of a 15V supply. The recording part consists of a LNA with a VCM of 7.5V and a supply voltage of ±1.65V around VCM - VDDLNA=9.15V and VSSLNA=5.85V. It consumes only 11.8μW and achieves an input referred root-mean-square (RMS) noise of 5.5μV in the frequency band of 1Hz to 100kHz. The design is implemented and simulated in a 0.18μm HV technology.

This paper considers the implementation of a continuous-time low-pass single-bit ΔΣ analog-digital converter (ADC) for radar applications. By taking advantage of the high transit frequency of a 0.25μm SiGe BiCMOS technology, the 3rd-order modulator operates at 1.92GHz and achieves 77.8dB SNDR within a bandwidth of 15MHz, when simulating the sensitive circuit parts on transistor level. Thanks to the inherent linearity of single-bit digital-analog converter (DAC), high linearity of 90dB spurious-free dynamic range (SFDR) can be achieved.

This paper presents the system level model of a transcutaneous optical telemetric link (TOTL) system for neural recording. Varieties of noise sources are characterized. Power distribution is described by means of Gaussian model approximation. Strategies for designing of the optical receiver that maximize signal to noise ratio (SNR) are discussed. The system level model presented here allows designers to compromise the TOTL receiver design for certain constraints: data rate, power consumption, thickness of tissue and receiver size.

In this paper we present a new architecture for PLL-based high-speed demodulation of frequency-modulated AFM signals. In our approach, we use single-sideband frequency up-conversion to translate the AFM signal from the position sensitive detector to a fixed intermediate frequency of 10 MHz. In this way, we fully benefit from the excellent noise performance of PLL-based FM demodulators still avoiding the intrinsic bandwidth limitation of such systems. Furthermore, the system becomes independent of the cantilever's resonance frequency. To investigate if the additional noise introduced by the single-sideband upconverter degrades the system noise figure we present a model of the AM-to-FM noise conversion in the PLL phase detector. Using this model, we can predict an upper corner frequency for the demodulation bandwidth above which the converted noise from the single-sideband upconverter becomes the dominant noise source and therefore begins to deteriorate the overall system performance. The approach is validated by measured data obtained with a PCB-based prototype implementing the proposed demodulator architecture.

In this paper, a novel model for single-bit internal quantizer SigmaDelta-modulators is presented. It is shown that this model can be used for an exact stability prediction of these systems. Furthermore, it is explained how the necessary computations can be performed in a numerically efficient way by means of a mixed integer linear program (MILP).

In this paper, a new methodology for the automated design of one-bit internal quantizer SigmaDelta-modulators is presented. The core of the method is an NTF prototype generation in the DT-domain based on the quasilinear quantizer modeling, that maximizes the maximum stable amplitude (MSA) of the modulator while achieving a certain minimum peak SNDR. For CT-modulator's, this is followed by a DT-CT mapping of the loop filter in state-space. The improved MSA allows for higher circuit noise and thus greatly relaxes the area and power consumption constraints of the design. Simulation results at the end of the paper verify the validity of the method.

AC sensitivities guide most analogue automatic test pattern generator (AATPG) while determining the optimal frequencies of a sinusoidal test stimulus. The optimal frequencies thus determined, normally lie in the close vicinity of the operating frequency of the circuit. Although these frequencies are justifiable by the principles of the circuit, these test frequencies do not bring any added value to the ultimate goal of cheap alternatives (low frequency test signal and cheaper measurement equipment) for the analogue and RF tests. In this paper, we propose to re-configure the circuit blocks, in such a way that the operating frequencies of the respective sub-block are shifted to lower testable frequencies. We have validated our proposal on a sub-block of a satellite receiver circuit that resulted in lowering the test frequencies of the corresponding sub-blocks from 12 GHz to 4MHz, while attaining the same level of defect coverage

In this paper an exact state equivalency including the input signal between continuous-time (CT) ΣΔ modulators and their discrete-time (DT) counterparts is derived. The equivalency is then generalized to include the very important non-ideal effect of excess loop-delay, that plays a crucial role in continuous-time modulators. With this new state-space equivalency, an efficient tool for stability analysis based on continuous-time describing functions is introduced. In the end, it is explained how these findings can be used for a MATLAB toolbox for continuous-time modulators that complements the well-known Schreier-toolbox for discrete-time modulators.

The phase-locked loop (PLL) has become one of the most commonly used circuits in electrical engineering nowadays. Therefore, there is a great need for both a solid mathematical theory, especially in the presence of noise, and practical design rules that help the PLL designer to improve the circuit performance. Although numerous papers have been published on both issues separately, there is still a huge demand to make the, often times rather advanced, mathematical theory of stochastic differential equations, needed to accurately model the noise in PLLs, more accessible for the circuit designer with merely a basic background in stochastic calculus. This paper is intended to show that, thanks to the performance of modern personal computers, one can derive results with accuracy comparable to the ones obtained from the so called Fokker-Planck technique using a Monte-Carlo simulation approach that can be understood and used in practice with merely an average background in probability