This paper presents an external compensation system for QHD+ ($3040\times1224$) mobile active-matrix organic light emitting diode (AMOLED) displays at a frame rate of 60 Hz. During vertical blank periods, current sensing AFE (CS-AFE) measures OLED currents to calculate threshold voltage ($V_{TH}$) of driving thin-film transistors (TFTs). For precise$V_{TH}$calculation against panel ground noise, a differential sensing scheme with 5-bit programmable capacitor array (PCA) is employed. In addition, digital correlated double sampling (CDS) removes an offset of the CS-AFE. However, recent advances in high efficiency OLED technology have led to increase in pixel density as well as the driving TFTs to operate close to subthreshold region. Therefore, the$V_{TH}$calculation based on the quadratic model yields inaccurate results. To compensate for the modeling error, we propose an error correction algorithm, which establishes an error function using a relationship between the modeling error and calculated threshold voltage during the manufacturing process. The proposed external compensation system was verified using CMOS-modeled three transistors and one capacitor (3T1C) pixel circuit. The test chip, fabricated in a$0.18~\mu \text{m}$BCD process, comprises 26 channels. Each channel consumes 78$\mu \text{W}$and occupies 1350$\times 50\,\,\mu \text{m}^{2}$. Measurement results show that current error at$64^{\mathrm {th}}$gray level is reduced from 35.56 LSB to 6.03 LSB after error correction and four frames average.

This paper presents a triple-band radio frequency (RF) energy harvesting system with 99.99% peak tracking efficiency and the triple band rectifier achieves the 4.6% improvement in the power conversion efficiency (PCE). The proposed system has a power range of −11 to 7 dBm with the three bands targeted on 900, 1900, and 2400 MHz. In this paper, the voltage and power characteristics of the triple-band rectifier at each band are extracted as raw data by measurement. The DC-DC boost converter is applied to achieve the maximum power point tracking (MPPT), which exploits the hill-climbing MPPT method. The method is implemented with register logics and power calculator. The converter’s voltage range of 0.1V to 2V is achieved, and the converter facilitates to achieve the highest tracking efficiency of 99.99%, 98.57%, 99.85% at each bands. The performance is verified through experimental results showing PCE improvement and over 87% tracking efficiency in a wide power range at triple bands. The triple-band rectifier with transmission line is fabricated on FR-4 substrate with active area 35.7 cm2, and the DC-DC boost converter with MPPT is implemented in a$0.18~\mu \text{m}$CMOS process with an active area of 0.94 mm2.

This paper proposes a fingerprint scanning analog front-end (AFE) for a$41\times32$under-glass mutual-capacitive fingerprint sensor. As the mutual-capacitive fingerprint sensor is a smaller version of a projected-capacitive touch screen, this transparent fingerprint sensor can be mounted underneath screen cover glass. However, such glass significantly diminishes the signal-to-noise ratio (SNR) of fingerprint scanning AFE in proportion with increasing glass thickness. Moreover, external noise interferences from the display and charger are severe in displays with thin form factor. The proposed fingerprint scanning AFE can achieve a 17 atto-farad capacitance resolution using high-voltage (20 V) transmitters and multi-channel receivers comprising a pipelined readout amplifier, mixer, and second-order low-pass filter (128 kHz). A differential sensing structure and band-pass filtering are employed in the receiver front-end to enhance the noise immunity. A differential phase-encoded sequential driving transmitter with a proposed on-chip replica channel mitigate random offsets in the readout amplifier with high matching accuracy. Measurement results show that the fingerprint scanning integrated circuit (IC) fabricated by a$0.18 ~\mu \text{m}$BCD (Bipolar-CMOS-DMOS) process achieved a 13.4 dB SNR at a frame rate of 120 Hz under a 0.2 mm-thick cover glass. The prototype IC provides 20 VPPnoise immunity from 0 to 500 kHz and consumes 23.2 mW from a 3.3 V supply.

This paper presents a wide input range active rectifier using a bipolar-CMOS-DMOS (BCD) process with a high voltage conversion ratio (VCR) and high power conversion efficiency (PCE). The proposed rectifier ensures safe and robust operation under large input voltage variations, which can be caused by changes in the magnetic coupling or loading conditions. It supports an input voltage range 3-12 V with the adaptive delay-compensated active operation of the power switches. An active signal clamper and voltage-time hybrid gate control circuit with two compensation loops was proposed for the optimal gate transition of low-side NMOS switches. For high-side PMOS switches, a fully integrated low-power-consuming high-side driver is proposed to replace the conventional high-side gate driving structure. The proposed active rectifier was fabricated through a TSMC 0.18 μm BCD process. The measurement results show that the proposed rectifier achieves stable and well-delay-compensated active operation, resulting in a high VCR and PCE with a wide output power range from 4.5 to 288 mW. Peak VCR and PCE of 96.8% and 93.7%, respectively, were achieved.

This paper presents a highly sensitive fingerprint readout IC for glass-covered mutual capacitive fingerprint sensor. To enhance signal to noise ratio (SNR) from the relatively loud noises compared to the signal, the proposed fingerprint readout IC uses modulation and demodulation process, band-pass operation and differential sensing scheme. Furthermore, the proposed fingerprint readout IC make an interface with 250 dpi glass-covered mutual capacitive fingerprint sensor which is patterned with 42 transmitter (TX) electrodes and 32 receiver (RX) electrodes. An analog front end (AFE) achieves 42 dB SNR under 0.1 T (mm) cover glass and 38 dB SNR under 0.2 T (mm) cover glass. The test chip fabricated with 0.18 μm CMOS process consumes 28 mW from a 3.3 V supply.

We propose improved SNR through on-chip Differentially Modulated Signaling with High Voltage (HV) based on Time-Interleaved Sensing Method (TISM) in fingerprint sensing. Tx driver transmits the 0 to 20V-pulse output with proposed signaling into Fingerprint Sensor (FPS), in order to increase the signal to noise ratio (SNR). When capacitance difference of valley-ridge is 0.4fF, the proposed differentially modulated TISM (DM-TISM) signaling is achieved to greater SNR (3.3dB) than that of conventional TISM in performance of fingerprint sensor readout IC architecture, when noise transient is included. Tx driver consists of 4 identical channels. A chip size is 1.3 × 1.1 mm2and prototype is fabricated in 0.25-um BCDMOS process.

In order for adaptive filter design to achieve optimum performance, the latency around the loop needs to be exactly designed for each targeted data rates. Due to unforeseen parasitic effects, latency has been major design issues for adaptive filters design with decision feedback topologies. In this paper, a digitally controlled adjustable delay line IC is presented that can be tuned with 3-ps resolution with a modular-based digital-to-analog converter (DAC) design. The proposed adjustable delay line achieved wide bandwidth for 10-Gb/sec data throughput while demonstrating bit-error rate (BER) improvement for the given equalizer design over various band-limited channels. The proposed IC is implemented in a 0.18-mum standard CMOS technology.

In this paper, a BiCMOS equalizer using an active delay line structure for backplane communication is investigated. Equalization is achieved using a finite impulse response (FIR) filter. The filter is implemented using variable gain blocks and delay elements. The variable gain function is implemented using a Gilbert cell topology, modified for high-speed application. The delay line is implemented using active devices. The active delay line consumes less area than a passive L-C delay line, and has improved bandwidth as well as performance over process variation. The equalizer is implemented in a 0.25-mum BiCMOS technology. To the best our knowledge, it is the first BiCMOS equalizer using an active delay line approach.

In order to realize adjustable equalization over various backplane channel configurations, a reconfigurable fully-integrated equalizer IC is presented. Backplane channels over different trace lengths and dielectric materials were measured and characterized. Feed-forward equalizer (FFE) topology with finite impulse response (FIR) architecture was chosen for optimal equalization for the corresponding backplane configurations. For a reconfigurable FFE IC implementation, wide-range tunable active delay line, variable tap-gain multiplier and 8-bit digital-to-analog converter (DAC) were fabricated in a 0.18-mum standard CMOS technology. The proposed reconfigurable FFE demonstrated successful equalization at 10Gb/sec over various channel configurations