The increase in the complexity of a wide-issue processor with its pipeline width is one of the primary concerns of processor designers. In the conventional design, the hardware in the processor core is laid out to handle multiple instructions with two source operands in each pipeline stage. However, an analysis of SPEC2000 programs reveals that an integer program on the average constitutes 25.2 percent of two-op (both source registers) integer instructions and 72.5 percent of one-op/zero-op integer instructions. Floating-point (FP) programs are found to constitute on the average 15.8 percent of two-op integer instructions and 44.1 percent of one-op/zero-op integer instructions. The analysis observes that the hardware laid out for worst-case requirements in the integer pipeline is highly underutilized for a significant portion of time. To alleviate the complexity issues, we propose the split pipeline architecture, a novel technique to distinguish and process instructions based on their source operand requirements. The conventional pipeline is split into two after the decode stage, and the two pipelines are again converged at the execution stage. This leads to a capability of processing instructions at a higher clock rate and at almost the same instruction-per-cycle (IPC) throughput, as compared to a conventional processor. Various flavors of the proposed architecture are simulated and analyzed in this paper, with a circuit level analysis to determine the impact on the critical path delays. Results show that a processor that can fetch, decode, and commit eight instructions in each cycle and with split pipelines of two two-source integer instruction and six zero/one-source integer instruction can achieve a clock rate that is 15.8 percent faster than an eight-wide conventional processor while reducing the IPC throughput by only 0.7 percent for SPEC2000 benchmarks. Similarly, a four-wide processor with split pipelines of one two-source integer instruction and three zero/one-source integer instructions can achieve a clock rate that is 19.69 percent faster than a four-wide conventional processor while reducing the IPC throughput by only 1.9 percent.

The increase in the circuit complexity of a wide-issue processor with its pipeline width is one of the primary concerns of the processor designers. In the conventional design, hardware in the processor core is laid out to handle multiple instructions with two-source operands in each pipeline stage. However, analysis of characteristics of the SPEC2000 integer programs reveals that 74% of instructions require one or less source register operands, and FP programs on average have 60% integer instructions three-fourth of which require one or less source register operands. To alleviate the complexity issues we propose split pipeline architecture, a novel technique to distinguish and process integer instructions based on their source operand requirements. This leads to a capability of processing instructions at a higher clock rate and at almost the same IPC, as compared to a conventional processor.

Current day wide-issue processors require the fetch engine in the frontend to continuously supply instructions to the issue queue in the backend to extract maximum possible amount of instruction level parallelism (ILP). Further, due to the continuous access of level-1 instruction cache (IL1) for fetching instructions, the power dissipation due to switching activity in IL1 is overwhelmingly high and continuous, and hence IL1 is one of the prominent hot-spots on the chip. In this paper, we alleviate the effect of control dependencies whenever a branch instruction forms a small loop. We use replicator architecture, a novel mechanism to supply twice the number of loop instructions in the same cycle, leading to a faster supply of instructions to the backend. This leads to an improvement in processor throughput in terms of instructions committed per cycle (IPC) due to extraction of higher ILP. Further, the mechanism results in a significant reduction in the total number of IL1 accesses. Implementation of the proposed technique in an 8-wide out-of-order issue processor results in a 19% improvement in IPC, and a 8.5% reduction in overall energy consumption on average, for various processor evaluation benchmark programs. Further, an enhanced Replicator mechanism results in larger reduction in IL1 accesses, leading to a 16% reduction in the overall energy consumed. The enhanced architecture removes the continuity in the access to the IL1 by feeding the instructions to the backend all by itself whenever a loop occurs. This gives a break to switching activity in IL1 and hence mitigates the hot-spot problem in the frontend of the processor.