This paper presents an enhanced current-reuse cascode Darlington broadband power amplifier using the cost effective tsmc${ }^{\text {TM }} 90-\text{nm}$CMOS process. It employs a modified Darlington architecture and a transmission-line transformer for ultra-broadband performance. Measurements show a 16.4 dB small-signal gain with a 3-dB bandwidth of$27 \text{GHz}(33-60 \text{GHz})$, achieving a$\mathbf{5 8 \%}$fractional bandwidth. The amplifier delivers a wideband flat saturated output power ($\boldsymbol{P}_{\text {sat }}$) of$9.9 \pm 0.6 \text{dBm}$from 35 to 60 GHz. The total chip area is only$0.82 ~\text{mm}^{2}$.

This paper presents the broadband communication capability of a millimeter-wave (mmWave) ultrawideband tightly coupled array (TCA) antenna based on high-density interconnect (HDI) antenna-in-package (AiP) technology. The essential antenna array elements are crafted using glass-based integrated passive devices (IPDs) and are subsequently flip-chipped on a multilayered HDI printed circuit board (PCB). The antenna features a wide impedance bandwidth from Ka- to W-band, suiting applications that demand a large signal bandwidth.

In this paper, a cryogenic low noise amplifier (LNA) consisting of three common-source stages is designed in a 70-nm GaAs metamorphic high electron mobility transistor (mHEMT) process for quantum computer applications. By using a cryogenic HEMT model, this LNA operates at 4 K and features wide bandwidth and high gain. It applies a filter input matching network and a bandwidth extension topology in the input and interstage matching, respectively. Characterized over the frequency range of 4 to 7 GHz, the LNA demonstrates a high gain level of 28.6 ± 2 dB with power consumption of 7.2 mW. In the low-power mode, it still maintains a gain level of 21.3 ± 1.2 dB with power consumption of 1.9 mW.

In this paper, a D-band low noise amplifier (LNA) is designed at the operation frequency of 140 GHz in a 70-nm GaAs metamorphic high electron mobility transistor (mHEMT) process. The three-stage cascode and one-stage common-source LNA is proposed to achieve wide bandwidth, low noise and high gain. Impedance matching is designed by using T-shape and dual T-shapes networks in the input, output and interstage matching. Passive devices are electromagnetically characterized at such a high frequency, including series capacitors and bypass networks. The LNA exhibits simulated average gain of 26.7 dB, global noise Figure below 6.1 dB, and bandwidth of 40 GHz. The input and output return loss are better than 13 dB and 9 dB, respectively. The power consumption is only 28 mW. The layout of the circuit occupies the area of $1.85 \times 1.4 mm^{\mathbf{2}}$.

A W-band low-noise amplifier consisting of seven common-source transistor stages is designed using noise measure as the figure of merit for circuit optimization. Fabricated in 90 nm CMOS technology, the die size is 0.38 mm2, while the core active area only 0.1 mm2. The circuit gives peak power gain of 21.5 dB at 90 GHz and noise figure of 8.3 dB, with dc power consumption of only 6.8 mW.

This paper presents analysis and design of source inductance for multistage LNA at 77-GHz band in 90 nm CMOS technology. Instead of simultaneous noise and impedance matching, the analysis shows the optimum degeneration of the single stage design for millimeter-wave frequencies. A low-power 77-GHz band LNA has been demonstrated to verify the optimization result. By using the proposed method, the LNA exhibited a low noise figure of 5.1 dB and a gain of 18.1 dB at 78.5 GHz with only 8 mW from a 1-V power supply.

A low-voltage and low-power CMOS mixer with an active balun is designed for frequency down-conversion in ultra-wideband applications. The mixer contains CMOS amplifiers as the LO buffer and the modulating stage in a folded configuration to allow low-voltage operation. The RF input signal comes from a new low-power active balun that uses a pair of common-source NMOS and common-gate PMOS transistors. This balun gives an impedance transformation ratio of 1:2, and provides a differential signal within 0.5dB and 1.5/spl deg/ of gain and phase imbalance, respectively, from 6 to 10.6-GHz. The mixer and the active balun are designed in 0.18/spl mu/m CMOS technology to operate at 1.2-V supply voltage. The circuit performance of the mixer with the active balun achieves flat conversion gain of 17 dB within 1 dB variation, the maximum IIP3 of 0 dBm, and the minimum noise figure of 13 dB. The total circuit only consumes power of 2 mW. As compared to typical designs, it saves about 85% and 95% of power consumption in the balun and the mixer circuits, respectively.

A fixed-width multiplier using the left-to-right algorithm for partial-product reduction is presented. The high-speed feature offered by this design is used to trade for low power. In one design, the proposed multiplier not only owns 8 % speed improvement but also gains 14 % power and 13 % area reduction. When applying the voltage scaling to balance the speed, the power reduction is increased to 29%. Categories and Subject Descriptors