Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Sergio A. Cannas

dblp:11/5485 · also Sergio Alejandro Cannas · DBLP profile ↗
← Back
5ranked-venue papers
1as first author
0since 2021 · last 2016
0000-0001-7331-3532ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 4 · 1 first-authorSystems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 33% Performance modeling and evaluation · 33% High-performance computing · 33%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Computational science and engineering · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs
FPGA accelerator
0.212016
FPGA Hardware Acceleration of Monte Carlo Simulations for the Ising Model · IEEE Trans. Parallel Distributed Syst. 2016
High-performance computing
ising model simulation
0.212016
FPGA Hardware Acceleration of Monte Carlo Simulations for the Ising Model · IEEE Trans. Parallel Distributed Syst. 2016
Performance modeling and evaluation › simulation
monte carlo simulation
0.212016
FPGA Hardware Acceleration of Monte Carlo Simulations for the Ising Model · IEEE Trans. Parallel Distributed Syst. 2016
Computational science and engineering › statistical physics
statistical physics simulation
0.112016
FPGA Hardware Acceleration of Monte Carlo Simulations for the Ising Model · IEEE Trans. Parallel Distributed Syst. 2016

Methods — techniques the papers use, named apart from their topics

hardware logic design · 0.5LFSR random number generation · 0.5
YearPublicationVenuePosition
2016 FPGA Hardware Acceleration of Monte Carlo Simulations for the Ising Model
abstract
A two-dimensional Ising model with nearest-neighbors ferromagnetic interactions is implemented in a Field Programmable Gate Array (FPGA) board. Extensive Monte Carlo simulations were carried out using an efficient hardware representation of individual spins and a combined global-local LFSR random number generator. Consistent results regarding the descriptive properties of magnetic systems, like energy, magnetization and susceptibility are obtained while a speed-up factor of approximately six times is achieved in comparison to previous FPGA-based published works and almost$10^4$times in comparison to a standard CPU simulation. A detailed description of the logic design used is given together with a careful analysis of the quality of the random number generator used. The obtained results confirm the potential of FPGAs for analyzing the statistical mechanics of magnetic systems.
Francisco Ortega-Zamorano, Marcelo A. Montemurro, Sergio A. Cannas, José M. Jerez, Leonardo Franco
IEEE Trans. Parallel Distributed Syst.3
2001 Generalization properties of modular networks: implementing the parity function
abstract
The parity function is one of the most used Boolean function for testing learning algorithms because both of its simple definition and its great complexity. We construct a family of modular architectures that implement the parity function in which, every member of the family can be characterized by the fan-in max of the network, i.e., the maximum number of connections that a neuron can receive. We analyze the generalization ability of the modular networks first by computing analytically the minimum number of examples needed for perfect generalization and then by numerical simulations. Both results show that the generalization ability of these networks is systematically improved by the degree of modularity of the network. We also analyze the influence of the selection of examples in the emergence of generalization ability, by comparing the learning curves obtained through a random selection of examples to those obtained through examples selected accordingly to a general algorithm we (2000) recently proposed.
Leonardo Franco, Sergio A. Cannas
IEEE Trans. Neural Networks2
2000 Generalization and Selection of Examples in Feedforward Neural Networks
abstract
In this work, we study how the selection of examples affects the learning procedure in a boolean neural network and its relationship with the complexity of the function under study and its architecture. We analyze the generalization capacity for different target functions with particular architectures through an analytical calculation of the minimum number of examples needed to obtain full generalization (i.e., zero generalization error). The analysis of the training sets associated with such parameter leads us to propose a general architecture-independent criterion for selection of training examples. The criterion was checked through numerical simulations for various particular target functions with particular architectures, as well as for random target functions in a nonoverlapping receptive field perceptron. In all cases, the selection sampling criterion lead to an improvement in the generalization capacity compared with a pure random sampling. We also show that for the parity problem, one of the most used problems for testing learning algorithms, only the use of the whole set of examples ensures global learning in a depth two architecture. We show that this difficulty can be overcome by considering a tree-structured network of depth 2log2(N)-1.
Leonardo Franco, Sergio A. Cannas
Neural Comput.2
1998 Solving arithmetic problems using feed-forward neural networks
Leonardo Franco, Sergio A. Cannas
Neurocomputing2
1995 Arithmetic Perceptrons
abstract
A feedforward layered neural network (perceptron) with one hidden layer, which adds two N-bit binary numbers is constructed. The set of synaptic strengths and thresholds is obtained exactly for different architectures of the network and for arbitrary N. These structures can be easily generalized to perform more complicated arithmetic operations (like subtraction).
Sergio A. Cannas
Neural Comput.1