High-safety automotive applications demand extensive trimming over a wide temperature range due to AEC-Q100 Grade 0 and ASIL-D requirements. To mitigate the trimming burden, this paper introduces a digitally self-calibrated RC oscillator (RCO) leveraging the Farey search algorithm (FSA) coupled with a fractional current-steering DAC (FIDAC) and a loop break (LB). The FIDAC generates denser trimming currents in a reduced area, while the FSA optimizes the FIDAC settings. The dynamic LB ensures the connection between the RCO and its reference during calibration phases, and isolation during normal operational states for cross-validation. The prototype RCO fabricated in 180nm CMOS process achieves 0.55%$3\sigma $-inaccuracy (280 samples) for process variations and 0.56%$3\sigma $-inaccuracy (56 samples) across −40°C to 150°C, meeting the AEC-Q100 Grade 0 temperature range requirement without manual trimming and fulfilling the ASIL-D isolation criteria.

Light detection and ranging (LiDAR) sensors enable precision sensing of an object in 3D. LiDAR technology is widely used in metrology, environment monitoring, archaeology, and robotics. It also shows high potential to be applied in autonomous driving. This paper proposes a Read-out Integrated Circuit (ROIC) for Optoelectronic mixer based LiDAR system design and fabricated in a standard 65nm CMOS technology. The proposed ROIC consisted of a wide bandwidth, high frequency Analog Front-End (AFE) and a long-range, low complexity Time-to-Digital Converter (TDC) stage. The AFE is designed with a wide bandwidth from 10MHz to 11GHz with the input referred noise level of $5.6\mu A/\sqrt {Hz} .$. Besides, a long range, low complexity and low resolution TDC stage is implemented with the performance that can reach the maximum measurable distance of 92.1m with the distance resolution of 1.66cm. All components of the proposed ROIC are fully integrated on-chip, occupying an area of 0.85μm2, with a measured power consumption of 31.76mW.

This paper presents an inductor-less, low-power, wideband, and noise-cancelling low-noise amplifier (LNA) for simultaneous deployment in low-power and multi-standard applications. The main novelty of this work lies in the concurrent utilization of the feedforward and feedback techniques to achieve simultaneous noise and distortion cancellation of input CG stage and bandwidth extension while maintaining low-power input matching, respectively. The proposed LNA is analyzed using the two-port network theory, thereby highly simplifying the extraction of device parameters and evaluating optimum design conditions. The proposed LNA is fabricated in a standard 65-nm CMOS process and occupies a core area of only 0.011-mm$^2$while consuming 960-$\mu$W of dc power from a 0.78-V supply. The peak$S_{21}$of LNA is 15.6 dB with a higher cut-off bandwidth ($BW_{-3dB}$) of 4.2 GHz. The minimum NF of LNA is 4.45 dB at 2 GHz, while the measuredIIP$_3$of the LNA is -16 dBm at the same frequency. Based on the measured data, the proposed LNA provides the widest bandwidth among the works reported in the low-power, inductor-less regime along with one of the highestFOM$_{I}$and a competitiveFOM$_{II}$.

This paper proposes the application of compressive sensing (CS) to reduce the measurement time in electrochemical impedance spectroscopy (EIS) for lithium-ion batteries. EIS is a non-destructive frequency response technique that provides valuable information on the state and degradation mechanisms occurring inside a battery. However, EIS measurement time is lengthy, making it impractical for evaluating the state of operating cells. CS is a signal-processing technique that enables the efficient acquisition and reconstruction of signals from a reduced number of measurements. The study aims to identify a suitable transform domain using dictionary learning that facilitates the adoption of CS techniques for the compression of the EIS data obtained from lithium-ion batteries. Thanks to the reduced number of EIS measurements, the proposed CS-based EIS achieves approximately 40% reduction in measurement time for open-source and in-house collected data, respectively, with minimal accuracy degradation.

Lithium plating poses a significant challenge to the performance and safety of lithium-ion batteries. As a non-destructive detection method, voltage relaxation profile (VRP) analysis shows great potential for effective lithium plating detection. However, the conventional VRP analysis suffers from a lengthy experimental time requirement, which fundamentally hinders the further development of the VRP-based detection. To overcome this limitation, this paper proposes a new lithium plating indicator by fully exploiting distinctive behaviors of differential voltage$(dV/dt)$profiles depending on the amount of lithium plating. The proposed indicator focuses on a local maximum value in the$dV/dt$profiles, which allows for achieving robust and fast prediction under cell-to-cell variation and aging while preserving the quantitative information obtained from the conventional detection. Based on experiments using battery cells, the adoption of the proposed indicator reduces the lithium plating detection time by 40% with a minimum error compared with the conventional method. Furthermore, applying the same approach to reference datasets further validates the efficacy of the proposed indicator across various conditions, including varying charging currents and temperatures, which confirms the reliability and accuracy of the proposed fast lithium plating detection.

Unmanned Aerial Vehicles (UAVs) are a promising application to deal with diverse industrial and social problems. In order to increase the utilization and reliability of UAVs, batteries play a big role. The flight feasibility evaluation of UAVs should be done in terms of battery before starting the flight missions. The properties of batteries are sensitive to temperature since they generate power through an electrochemical reaction. In this paper, a battery temperature estimator is presented for a system-level UAV flight evaluation considering the usability of end-users. The proposed estimator consists of flight history-aware data preprocessing and a deep neural network-based model instead of the conventional physics-based approach that requires in-depth theories. The flight data is collected through the actual flight experiments of a UAV for training and validation. The proposed method achieves a temperature estimation error of less than$2.02^{\circ}\mathrm{C}$compared with the actual measured data of a UAV battery. The effectiveness of the proposed estimator is presented by case studies.

Electrochemical impedance spectroscopy (EIS) is a non-invasive method for analyzing battery states based on impedance measurements. With the widespread use of high-capacity lithium-ion batteries in the range of mΩ impedance, achieving highly accurate impedance measurements becomes crucial for precise battery examination. EIS systems frequently utilize a digital lock-in amplifier (DLIA) to achieve ultra-precision impedance readings, but it requires a long settling time. This study proposes an innovative EIS architecture with a two-stage Hilbert transform that significantly reduces the measurement time by widening the bandwidth of noise suppression low-pass filter while maintaining high accuracy. It achieves a substantial 66% reduction in the estimated settling time at the lower bound frequency of 1 Hz and a 57% reduction in the total measurement time across the frequency range of 1-to-1k Hz.

This study presents a novel method that combines dV/dQ curves and entropy profiles to accurately delineate the phase transition boundaries of battery electrodes. This integration provides a comprehensive understanding of the phase transition behavior, enabling precise identification of phase change boundaries. Employing these boundaries, phase-based capacity loss tests are conducted under galvanostatic aging cycles, allowing for the observation of battery aging characteristics across different aging ratios. The findings obtained from these tests offer valuable insights into the aging mechanisms and performance degradation associated with specific phases. Consequently, this research enables the development of strategies to optimize the charging scheme, mitigate capacity loss, and enhance battery performance, ultimately leading to a prolonged battery lifespan. Overall, this study contributes to advancements in accurately characterizing phase transitions, optimizing charging schemes, and improving the overall performance and longevity of batteries.

This paper presents a self-startup power management IC (PMIC) applicable in thermoelectric generators (TEGs). The PMIC is based on a boost converter integrated with a complete control circuitry that handles all required operations, including maximum power point tracking (MPPT). The converter supports cold self-start from low TEG voltages using three startup phases and two power-on-reset (POR) signals for smooth transitions between the phases. The PMIC is designed and fabricated in a 180-nm technology. The cold-start operation is verified at a minimum TEG voltage of 60 mV. The converter achieves a peak efficiency of 79.94% at 120-mV input voltage and 1080 μW output power, while maintaining efficiency above 70% for a wide range of TEG voltage from 80 mV.

This paper presents an ultra-low power, high-sensitivity, and interference-resistant receiver suitable for IoT applications. By the combination of sliding-IF based low-power down-conversion and relative-power-detection based FSK demodulation, the proposed receiver achieves multi-channel operation and minimizes power consumption. Cascaded N-path filter and 4th-order hybrid-PPF are adopted to improve the sensitivity and carrier-to-interference ratio. Implemented in a 65nm CMOS, the receiver achieves -102dBm sensitivity at 0.1% BER while consuming 466μW from a 0.6V supply.

A dual-peak maximum achievable gain core design technique is proposed. It has been adopted into a 4-stage wideband amplifier. Implemented in a 65nm CMOS, the amplifier achieves 3dB bandwidth of 30GHz (230~260GHz), gain of 12.4±1.5dB, and peak PAE of 1.6% while dissipating 23.8mW, which corresponds to the widest bandwidth and highest gain per stage among other reported CMOS amplifiers operating above 200GHz.

This paper presents a self-powered rectifier for piezoelectric energy harvesting applications, and the key idea of the proposed system is to reset the transducer capacitor at optimal instants to maximize the extracted power. The proposed rectifier consists of two switches and two active diodes. The switches discharge the transducer capacitor at optimal instants two times for every cycle. The active diodes are based on op-amps with a preset dc offset, which reduces the voltage drop and the leakage current and avoids instability. In addition, the controller for the proposed rectifier is simple to reduce the circuit complexity and the power dissipation. The proposed rectifier was designed and fabricated in 0.18-μm CMOS technology. Measured results indicate that it achieves power efficiency of 91.2%, and the amount of power extracted by the proposed rectifier is 3.5 times larger when compared with the conventional rectifiers. The proposed rectifier does not require any off chip components to enable a full chip integration, and the die area of the proposed circuit is 0.08 × 0.20 mm2.

In this paper, an accurate, low power CMOS temperature sensor for attachable medical devices (AMDs) is presented. The proposed temperature sensor consists of a high-slope proportional to absolute temperature (PTAT) current and reference voltage generator, a current controlled relaxation oscillator (ICRO), a digital counter, and a reference clock generator. By adopting a temperature conversion linearity compensation technique, simulation results show -0.10 °C ~ +0.13°C temperature inaccuracy in a range of 20°C ~ 50°C with a 100 samples/s sampling rate. The presented sensor dissipates 2uW under 1.2-V supply in a 0.13um CMOS technology.

This paper discusses design challenges and strategies for aggressively increasing energy efficiency of biosignal monitoring sensors. For the holistic understanding of energy efficiency, we introduce Energy Efficiency metric for all sensor communication blocks which include not only Rx/Tx RF&Analog, PLL and DSP/Modem but also Antenna and Power Management. Based on the metric, an ultra-low energy sensor node design at 2.36~2.5GHz is addressed from RFIC, DSP/Modem to Antenna. To tackle the stringent power requirements, we theoretically revisit the technology, circuits, architecture and system and explore the cross-layer power minimization algorithm.

A low power dual-channel asynchronous successive approximation register (ASAR) analog-to-digital converter (ADC) is presented. A metastable-then-set (MTS) algorithm is proposed with the aim of eliminating unnecessary decision operations in ASAR and its effects on power consumption and performance have been measured. The proposed flag synchronization technique minimizes the crosstalk between two asynchronous ADCs. A prototype ADC was implemented in 0.13-μm CMOS technology and operated under a 1.2 V supply. At a sampling rate of 17.5 MS/s, the ADC achieves a peak signal-to-noise and distortion ratio of 51.3 dB at 1.73 MHz input frequency. The measured total power dissipation of a single channel ADC is 570 μW and the figure of merit is 103 fJ/step.

In this paper, a low power, low flicker noise and high IIP3 I/Q mixer for 76-108MHz EURO/US/Korea/Japan FM radio receiver applications is presented. The proposed mixer includes a transconductance (Gm) stage, a current mode passive switching stage driven by a 25% duty cycle LO, a transimpedance amplifier (TIA), and a 25% duty cycle LO generator. Simulation results show a 9.2dB DSB noise figure at 50kHz, 13dBm IIP3, and 23dB voltage gain, respectively, while drawing only 800uA including a LO generator from a 1.2-V supply in a standard 65nm CMOS technology.

This paper presents a low-power coherent receiver for UWB pulsed radar for motion detection. Due to accuracy of the radar motion detection, coherent detection scheme is adopted in the receiver. To relax the stringent requirement of timing synchronization, sliding correlation detection is proposed. The clocking step which determines detection resolution is determined by 2 ns which is half of a pulse width or equivalent to 30 cm. Receiver is designed in 0.13-mum CMOS process from 1.5 V supply. The pulse center frequency is 4 GHz. The receiver includes a high voltage gain LNA, a analog correlator, a sampling comparator and a flip flop. The whole receiver excluding an LNA consumes 0.9 mA of DC current and 10 pJ/pulse at the pulse rate of 16 MHz. The active size is 600 times 380 mum2.

This paper describes a wide-band sharp-rejection active-RC low pass filter (LPF) for pulse-based UWB IEEE 802.15.4a WPAN applications. Sharp rejection is attributed to the combination of different AC characteristic of three biquads in series. A simple operational amplifier (Op-amp) is adopted to ensure high frequency performance for the designed filter. The LPF is designed in 0.13µm TSMC CMOS process. The cutoff frequency is 380MHz with about 50% of the tuning range from 300–500MHz. The rejection is 40 dB at 600 MHz. The passband ripple is less than 1.5dB and the filter consumes 4.6mA from 1.2V supply. Core chip size is 580 × 700µm2.

This paper presents an alternative topology for realizing a four-quadrant amplifier with single-ended output. In the proposed multiplier, constituting differential circuits are vertically arranged resulting in single-ended current output with output DC voltage equal to a half of supply voltage. Since the circuit operates in a current-reused mode, the power consumption is systematically reduced by a factor of 50% compared to the original topology. The proposed multiplier is designed based on a 0.18 mum CMOS process and can operates under a 1.2 V supply.

This paper presents an ultra low-power, low-complexity circuit to generate the monocycle pulse for Impulse Radio UWB (IR-UWB) applications. A 7th order derivative Gaussian pulse is generated using the edge combination technique plus an extra derivative circuitry. The proposed pulse generator is designed using TSMC 0.18 μm CMOS process. Simulation shows 500 mV of pulse amplitude and 800 ps of the pulse duration. Generated pulse spectrum fully complies with the FCC spectrum mask for out-door applications, especially in the range of 3.1-5.1 GHz. The pulse generator dissipates no static current with only dynamic energy consumption of around 4.7 pJ per pulse from 1.5 V supply.

A newly proposed variable gain amplifier (VGA) that offers wide bandwidth and gain variation characteristics is described for ultra wideband system applications. The proposed VGA combines a cascade-input stage and bandwidth-extension loads to obtain a wide bandwidth. The VGA is simulated in 0.13 /spl mu/m CMOS technology and simulations show a gain variation range of 54 dB in a single-stage VGA and a minimum 1-dB bandwidth of 743 MHz at the maximum gain of 20 dB. The 1-dB bandwidth improvement of 58% compared to conventional VGAs at the same supply current is obtained. In addition, the newly proposed control stage results in a compact VGA, which leads to low power consumption. The VGA dissipates an average supply current of 4.5 mA from 1.8 V supply voltage.

This paper presents a low power high linearity transmitter front-end for 900 MHz Zigbee applications based on 0.18 /spl mu/m CMOS technology. The direct up-conversion is implemented by passive mixer which dissipates no DC current. Two stage driver amplifiers provide high enough gain as well as high linearity to drive high power signal to 50/spl Omega/ antenna while consuming small amount of current. Measurement shows 11.5 dB overall transmitter gain, 3 dBm output P1dB while dissipating 1.8mA DC current from 1.8 V supply.

This paper presents a new configuration for linear MOS operation transconductance amplifier (OTA) based on a standard 0.25 /spl mu/m CMOS technology. The proposed circuit combines two previously reported linearization techniques: source degeneration using MOS transistor and class AB linearization. Measured results show that the proposed circuit provides rail-to-rail differential input range. Total harmonic distortion of the proposed circuit is -60 dB at 5 MHz for 0.6-Vpp differential input voltage while dissipating only 25 /spl mu/W from 1.25 V supply.

This paper presents a sub-mA, low-noise, high-gain CMOS low noise amplifier (LNA) for 2.4-GHz band applications based on 0.18 /spl mu/m CMOS technology. Low-noise under power-constrained can be achieved by using an inductive cascode degeneration amplifier with an extra gate-source capacitor. Gain enhancement can be obtained by using capacitive feedback at the cascode transistor. Measurements show 16 dB gain, 1.8 dB NF, -10 dBm IIP3 while dissipating only 0.5 mA from 1.5 V supply.

This paper presents an I/Q down conversion mixer in the receiver of ultra-wide band (UWB) systems with gain mismatch compensation capability by integrating the two PMOS variable gain amplifiers (VGA) at the output. The I/Q mixer is designed in 0.18/spl mu/m Samsung CMOS technology. The proposed mixer operates at 1.584 GHz with the power conversion gain of 5.9 dB, IIP3 of 4.1 dB and NF of 7.9 dB. By adjusting the gain of VGA, the I and Q outputs perfectly have the same gain. LO-RF leakage is smaller than -72 dB. The designed mixer consumes total 11.5 mA from 1.8 V of supply voltage.

A multi-LO frequency synthesizer block for MB-OFDM UWB systems is proposed, which is implemented in 0.18 mum CMOS technology. The proposed frequency synthesizer can provide three LO tones and quadrature IF LO tone from only one VCO. Based on an optimized frequency plan, it uses fewest nonlinear components like divide-by-N and mixer to suppress unwanted spurious tones. Its measured in-band sideband suppression ratio is more than 30 dBc for three sub-bands and it consumes only 17.6 mA from a 1.8 V supply.

This paper represents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.

A CMOS voltage-to-current converter with exponential characteristic is presented in this paper. The concept of Taylor series expansion is used for realizing the exponential characteristic. The proposed exponential V-I converter is composed of a current-to-current squarer and a linear V-I converter with the use of linearization technique. Based on a 0.25 µm CMOS process, simulations show a 23 dB of linear-output current range and the linearity within 20 dB with error less than ± 0.5dB is achieved. The total power consumption is below 0.2 mW with 1.25 V supply voltage. The proposed circuit can be used for the design of an extremely low-voltage low-power variable gain amplifier (VGA).

Self-heating effects in bipolar junction transistors (BJTs) have been incorporated into PSpice DC and AC analyses. The effects are intrinsic to the operation of the transistor, and are treated within the device model, avoiding the need for thermal subcircuits. A physical thermal impedance model is provided, which allows prediction of the thermal impedance for devices with rectangular emitters from device geometry. A simple approximation is used to predict thermal frequency response. The predictive model can be overridden by measured thermal model parameters. The modifications made to the PSpice code are presented, along with some discussion of implementation alternatives. An example simulation is presented, demonstrating the significance of thermal effects in a typical circuits. Run-time comparisons show that the modified code is about half the speed of unmodified PSPice, mostly because of slower convergence. It is believed that this performance can be improved with suggested implementation changes.>