Demo Data from EDBT 2026 / reviewers in the wild / expert
D. S. H. Chan
dblp:11/575
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Performance modeling and evaluation · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design optimization |
0.0 | 1 | 2000 | Global optimization for digital MOS circuits performance · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Performance modeling and evaluation › numerical algorithms
global optimization |
0.0 | 1 | 2000 | Global optimization for digital MOS circuits performance · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Electronic design automation › design for manufacturability › design for yield
parametric yield optimization |
0.0 | 1 | 2000 | Global optimization for digital MOS circuits performance · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Methods — techniques the papers use, named apart from their topics
global approximation · 0.0genetic algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | Global optimization for digital MOS circuits performanceabstractApart from maximization of parametric yield, minimization of the spread in performance functions due to process variation is of extreme importance in very large scale integrated circuit design. To achieve efficient minimization of the spread, a novel algorithm based on the genetic algorithm and global approximation methods is proposed. The algorithm operates in two stages designated as coarse and fine optimization stages and adjusts design parameter set to simultaneously achieve the target performance and reduction in performance spread. The algorithm has distinctive features, such as global optimum design, subexponential complexity algorithm for N-P complete problem of global optimization, and simultaneous optimization of many functions. The algorithm is demonstrated using four design examples. H. M. Chen, G. S. Samudra, D. S. H. Chan, Yaacob Ibrahim |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1999 | Yield Optimization by Design Centering and Worst-Case Distance AnalysisabstractProcess variations invariably give rise to a parametric yield below 100% for VLSI circuits. Improving the yield by choosing a set of optimum parameter values does not incur any extra cost, and it is a preferred method as it directly translates into profits. The paper presents an efficient and novel method to improve the VLSI parametric yield by selecting optimum parameter values. This method utilizes the worst-case distance analysis, design centering and gradient-dependent techniques. One circuit example is presented to demonstrate the optimization scheme. G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim |
ICCD | 3 |