We present analytical expressions for MOSFET distortion as a function of inversion level, represented by gm/IDas a proxy. The expressions are particularly useful for moderate inversion, where the generic textbook equations fail. Unlike previous approaches, the method requires only a small number of technology parameters. For an estimation of gmnonlinearity, only the subthreshold slope is needed. Two additional parameters are required to model gdsnonlinearity. The derived expressions are validated based on SPICE simulations using a well-calibrated 65-nm PSP model set.

Redundancy in the output code, as instrument to reduce the impact of non-idealities in different architectures of two-step A to D converters, is investigated. A circuit model capable of providing an estimate of the required sizes for passive components for a given accuracy was developed. Such model represents an useful design tool, providing a way to calculate important figures of merit (area, power, ENOB, SNR, large-signal behavior) of the different ADCs. System-level simulation results are provided and discussed.

A design methodology for analog circuit blocks is proposed which combines circuit knowledge and high-level general-purpose math packages with CAD simulation tools. The proposed flow of the design of a complex analog or mixed-signal system starts with a conceptual phase setting performance goals for each block, Followed by an exploration phase based on analytical descriptions resulting in the selection of a performance point in the design space and an implementation phase resulting in the sizing of the transistors in each block. The final phase of the electrical design is verification, optimization and design centering in SPICE using foundry-provided process data. It is shown that numerical optimization available in some SPICE offerings such as Eldo deliver a design that not only meets specifications but delivers optimal performance for a selected objective within given constraints

A complete digitally-programmable analogue fuzzy logic controller (FLC) is presented. The design of some new functional blocks and the improvement of others aim towards speed optimisation with a reasonable accuracy, as it is needed in several analogue signal processing applications. A nine-rules, two-inputs and one-output prototype was fabricated and successfully tested using a standard CMOS 2.4 /spl mu/ technology showing good agreement with the expected performances, namely: 5.26 Mflips (mega fuzzy logic inferences per second) at the pin terminal (@CL=13 pF), 933 /spl mu/W power consumption per rule (@Vdd=5V) and 5 to 6 bits of precision. Since the circuit is intended for a subsystem embedded in an application chip (@CL/spl les/15 pF) over 8 Mflips may be expected.

Kohonen maps are self-organizing neural networks that classify and quantify n-dimensional data into a one- or two-dimensional array of neurons. Most applications of Kohonen maps use simulations on conventional computers, eventually coupled to hardware accelerators or dedicated neural computers. The small number of different operations involved in the combined learning and classification process, however, makes the Kohonen model particularly suited to a dedicated VLSI implementation, taking full advantage of the parallelism and speed that can be obtained on the chip. A fully analog implementation of a one-dimensional Kohonen map, with on-chip learning and refreshment of on-chip analog synaptic weights, is proposed. The small number of transistors in each cell allows a high degree of parallelism in the operations, which greatly improves the computation speed compared to other implementations. The storage of analog synaptic weights, based on the principle of current copiers, is emphasized. It is shown that this technique can be used successfully for the realization of VLSI Kohonen maps.

The binary picture processing and recognizing stages of an optical character recognition (OCR) system have been designed using both flexibility of available microprocessors and speed of peripheral custom-designed integrated circuits. A dedicated large-scale integrated (LSI) processor performs edge detection and thinning of a 32 × 24 digitized one-piece pattern. The output signal–a set of 3 bit vectors describing the skeletonized character contour–feeds a microprocessor which controls the character recognition algorithm including pattern segmentation, filtering, feature extraction, and classification decision. This low-cost equipment is especiaUy suitable for hand-carried OCR systems where well-formed printed alphanumerics are to be read. However, continously deformed patterns like carefully handprinted characters are recognized as well. A system reading speed of 100 characters/s (or 30 cm/s) can be achieved.