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Naresh M. Patel

dblp:11/618 · DBLP profile ↗
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7ranked-venue papers
2as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 first-authorSoftware engineering, systems software and programming languages · 3 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Storage systems · 40% Memory systems · 40% Cloud and datacenter computing · 12%

Topics — the 9 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
flash and SSD
0.112012
Performance implications of flash and storage class memories · SIGMETRICS 2012
Memory systems › non-volatile memory
storage class memory
0.112012
Performance implications of flash and storage class memories · SIGMETRICS 2012
Cloud and datacenter computing
cloud storage
0.012012
Performance implications of flash and storage class memories · SIGMETRICS 2012
Interconnection networks and networks-on-chip › switching network
multistage interconnection network
0.011990
The Representation of Multistage Interconnection Networks in Queuing Models of Parallel Systems · J. ACM 1990
Performance modeling and evaluation
queueing models
0.011990
The Representation of Multistage Interconnection Networks in Queuing Models of Parallel Systems · J. ACM 1990
Performance modeling and evaluation › queueing models
queueing network model
0.011990
The Representation of Multistage Interconnection Networks in Queuing Models of Parallel Systems · J. ACM 1990
Interconnection networks and networks-on-chip › network contention
hot-spot contention
0.011988
On Hot-Spot; Contention in Interconnection Networks · SIGMETRICS 1988
Interconnection networks and networks-on-chip
network contention
0.011988
On Hot-Spot; Contention in Interconnection Networks · SIGMETRICS 1988
Interconnection networks and networks-on-chip
interconnection networks
0.011988
On Hot-Spot; Contention in Interconnection Networks · SIGMETRICS 1988

Methods — techniques the papers use, named apart from their topics

performance analysis · 0.1simulation · 0.0decomposition technique · 0.0analytical modeling · 0.0
YearPublicationVenuePosition
2018 Optimizing Energy-Performance Trade-Offs in Solar-Powered Edge Devices
abstract
Power modes can be used to save energy in electronic devices but a low power level typically degrades performance. This trade-off is addressed in the so-called EP-queue model, which is a queue depth dependent M/GI/1 queue augmented with power-down and power-up phases of operation. The ability to change service times by power settings allows us to leverage a Markov Decision Process (MDP), which approach we illustrate using a simple fully solar-powered case study with finite states representing levels of battery charge and solar intensity.
Peter G. Harrison, Naresh M. Patel
ICPE2
2012 Performance implications of flash and storage class memories
abstract
The storage industry has seen incredible growth in data storage needs by both consumers and enterprises. Long-term technology trends mean that the data deluge will continue well into the future. These trends include the big-data trend (driven by data mining analytics, high-bandwidth needs, and large content repositories), server virtualization, cloud storage, and Flash. We will cover how Flash and storage class memories (SCM) interact with some of these major trends from a performance perspective.
Naresh M. Patel
SIGMETRICS1
2012 Storage workload modelling by hidden Markov models: Application to Flash memory
Peter G. Harrison, S. K. Harrison, Naresh M. Patel, Soraya Zertal
Perform. Evaluation3
2010 Response time distribution of flash memory accesses
Peter G. Harrison, Naresh M. Patel, Soraya Zertal
Perform. Evaluation2
1990 The Representation of Multistage Interconnection Networks in Queuing Models of Parallel Systems
abstract
A major component of a parallel machine is its interconnection network (IN), which provides concurrent communication between the processing elements. It is common to use a multistage interconnection network (MIN) that is constructed using crossbar switches and introduces contention not only for destination addresses but also for internal links. Both types of contention are increased when nonlocal communication across a MIN becomes concentrated on a certain destination address, the hot-spot . This paper considers analytical models of asynchronous, circuit-switched INs in which partial paths are held during path building, beginning with a single crossbar and extending recursively to MINs. Since a path must be held between source and destination processors before data can be transmitted, switching networks are passive resources and queuing networks that include them do not therefore have product-form solutions. Using decomposition techniques, the flow-equivalent server (FES) that represents a bank of devices transmitting through a switching network is determined, under mild approximating assumptions. In the case of a full crossbar, the FES can be solved directly and the result can be applied recursively to model the MIN. Two cases are considered: one in which there is uniform routing and the other where there is a hot-spot at one of the output pins. Validation with respect to simulation for MINs with up to six stages (64-way switching) indicated a high degree of accuracy in the models.
Peter G. Harrison, Naresh M. Patel
J. ACM2
1988 On Hot-Spot; Contention in Interconnection Networks
Naresh M. Patel, Peter G. Harrison
SIGMETRICS1
1987 The Representation of Switching Networks in Queueing Models of Parallel Systems
Peter G. Harrison, Naresh M. Patel
Performance2