Memristive technologies offer fascinating opportunities for unconventional computing architectures and emerging applications. While memristive devices have received substantial attention as sources of entropy for security applications, security vulnerabilities of memristive technologies for implementing cryptographic circuits have been largely neglected so far. In this article, we provide the first in-depth analysis of power side-channel analysis against memristive cryptographic implementations based on both: physical experiments and simulations. We show that power consumption models developed for CMOS are not fully adequate for memristive circuits. In particular, the memory effect makes even input-independent initialization cycles vulnerable to attacks that would be fundamentally impossible in CMOS technologies. We propose a memristive-oriented Power Estimation Model (mPEM) integrated into the Stochastic Approach (StA) framework and demonstrate its effectiveness against larger-scale circuits. Finally, we demonstrate that attack countermeasures that were effective for CMOS fail for fundamental reasons in the memristive case.

In the light of implementation attacks a better understanding of complex circuits of security sensitive applications is an important issue. Appropriate evaluation tools and metrics are required to understand the origin of implementation flaws within the design process. The selected leakage model has significant influence on the reliability of evaluation results concerning the side-channel resistance of a cryptographic implementation. In this contribution we introduce methods, which determine the accuracy of the leakage characterization and allow to quantify the signal-to-noise ratio. This allows a quantitative assessment of the side-channel resistance of an implementation without launching an attack. We validate the conclusions drawn from our new methods by real attacks and obtain similar results. Compared to the commonly used Hamming Distance model in our experiments enhanced leakage models increased the attack efficiency by up to 500%.

Side-channel analysis has become an important field of research for the semiconductor industry and for the academic sector as well. Of particular interest is constructive side-channel analysis as it supports a target-oriented associated design process. The main goal is to increase the side-channel resistance of cryptographic implementations within the design phase by a combination of advanced stochastic methods with design methods, tools, and countermeasures. In this contribution we present a new enhanced tool that utilizes symmetry properties to assist the side-channel evaluation of cryptographic implementations. This technique applies a symmetry metric, which is introduced as an engineering tool to verify the suitability of the leakage model in the evaluation phase of security-sensitive designs. Additionally, this approach also supports the designer in the selection of appropriate time instants.

We introduce a stochastic method for the security evaluation and dynamic power consumption analysis in the context of side-channel analysis. This method allows to estimate data-dependent power consumption induced by secret parameters, e.g. a cryptographic key, which may be exploited in power attacks. In particular, IP-cores for security applications on FPGAs have to be made secure against these attacks. We show that the same stochastic methods provide FPGA designers constructive feedback on the information leakage of the design. Applied as a constructive tool these stochastic methods allow the designer to quantify the side-channel resistance and weaknesses of the IP-core design, a feature which supports the design of secure and side-channel resistant implementations, especially on FPGAs.

Since the remarkable work of Kocher [7], several papers considering different types of timing attacks have been published. In 2003, Brumley and Boneh presented a timing attack on unprotected OpenSSL implementations [2]. In this paper, we improve the efficiency of their attack by a factor of more than 10. We exploit the timing behavior of Montgomery multiplications in the table initialization phase, which allows us to increase the number of multiplications that provide useful information to reveal one of the prime factors of RSA moduli. We also present other improvements, which can be applied to the attack in [2].

Random number generators are essential components of many cryptographic systems. Inappropriate random number generators may weaken the security properties of the system considerably. This paper considers evaluation criteria for true (physical) random number generators. General objectives are formulated and possible criteria and measures are discussed which shall ensure these goals. Central parts of the mathematical-technical reference of the German evaluation guidance document AIS 31 ([],[]) are cited and rationale is given.