Millimeter-wave (mmWave) systems require a large number of antennas, which makes the beam training challenging and time-consuming for conventional phased arrays. Recently, a true-time-delay (TTD) array-based beam training algorithm has been shown as an effective solution to overcome the training overhead in large arrays. In this paper, we present a custom-built over-the-air (OTA) testbed to study the effects of hardware impairments on the TTD-based beam training and verify its feasibility in a real system. We proposed an orthogonal matching pursuit (OMP) based reconstruction algorithm along with a phase calibration dictionary to combat nonidealities such as strong frequency selectivity and phase misalignment in the received raw IQ signal. Post-processing results showed that with the nonideality effects properly handled, the 3D TTD beam training algorithm can achieve high AOA estimation accuracy.

Increasing user density and capacity in next-generation systems presents a need for fine beam angle resolution especially in the emerging upper mid-band$7-24$GHz frequency regime. This paper presents a scalable area- and energy-efficient quadrature generator targeted for beamforming receivers with a multi-stage phase-shifting polyphase filter providing continuous beam angle resolution. When complemented with vector modulation for coarse tuning, a phase range of 360° is achieved realizing a phase-shifter-less implementation leveraging slice-based receiver architecture and polyphase filters. Fabricated in 65nm CMOS, the phase-shifting polyphase filter occupies 0.003 mm2, consumes 0.25 mW, and achieves an Image Rejection Ratio >58 dB over the entire phase range. The quadrature generator is demonstrated with a proof-of-concept receiver array operating between 7.28-7.78 GHz consuming 37 mW per element occupying 1.26 mm2.

Non-Foster (NF) circuits are becoming increasingly popular in filters and matching networks as they allow the cancellation of reactances and thus enable wideband matching. With many kinds of NF circuits available in the literature, this paper aims to categorize and provide an in-depth discussion of each variation of these circuits upon their implementation, advantages and challenges.

Future energy harvesting systems require ultra-low supply sensor interfaces operating at sub-0.4 V. Time-based sensor-to-digital interfaces, though compatible with ultra-low supply, are highly sensitive to inherent mismatch in the current-controlled ring oscillators (CCRO) especially in a multibit architecture. Contrary to a multi-bit sensor interface, this work realizes a single-bit system replacing the multi-phase CCRO with a nanoWatt current-controlled relaxation oscillator (CCRxO) and thus obviating the significant delay cell mismatch in the CCROs. In addition, we propose a time domain calibration loop (TDCL) to mitigate the high signal-to-noise and distortion ratio (SNDR) sensitivity related to the KVCOvariation with respect to supply. A pulse-biasing circuit is proposed for fast settling of the internal nodes and facilitate quick switching between calibration and data conversion modes. The proposed closed-loop single-bit VCO-based sensor-to-digital front-end with TDCL was fabricated in 180 nm CMOS technology. Operating under 0.35 V, the chip consumes a total power consumption of$0.22~\mu \text{W}$only with a SNDR of 63.2 dB. The SNDR variation is measured to be only 1.7 dB with more than 50% supply variation validating the effectiveness of the proposed TDCL.

The best beam steering directions are estimated through beam training, which is one of the most important and challenging tasks in millimeter-wave and sub-terahertz communications. Novel array architectures and signal processing techniques are required to avoid prohibitive beam training overhead associated with large antenna arrays and narrow beams. In this work, we leverage recent developments in true-time-delay (TTD) arrays with large delay-bandwidth products to accelerate beam training using frequency-dependent probing beams. We propose and study two TTD architecture candidates, including analog and hybrid analog-digital arrays, that can facilitate beam training with only one wideband pilot. We also propose a suitable algorithm that requires a single pilot to achieve high-accuracy estimation of angle of arrival. The proposed array architectures are compared in terms of beam training requirements and performance, robustness to practical hardware impairments, and power consumption. The findings suggest that the analog and hybrid TTD arrays achieve a sub-degree beam alignment precision with 66% and 25% lower power consumption than a fully digital array, respectively. Our results yield important design trade-offs among the basic system parameters, power consumption, and accuracy of angle of arrival estimation in fast TTD beam training.

This paper presents an integrated ultra-low-power (ULP) wireless sensor system-on-chip (SoC) that can be used for voltage sensing in both Internet of Things applications and bio-potential monitoring. In order to increase the energy efficiency of the analog front-end (AFE), we propose a noise and power efficient push-pull low noise instrumentation amplifier (LNIA) with a built-in ripple reduction loop based on capacitor reuse. A low-power ISM-band harmonic injection locked on-off-keying transmitter (OOK-TX) is also implemented for energy efficient wireless connectivity. Circuit implementations, design considerations, and detailed analysis are presented to improve the overall energy efficiencies of the SoC including the AFE, TX and, the power management unit. The proposed ULP-SoC is fabricated in 130 nm CMOS technology with a total area of 1.92 mm2. The total power consumption of the proposed system-on-chip is 197.1 μW which is one of the lowest among state-of-the-art wireless sensor SoC.

The development of an autonomous tracking system which could accurately locate and transfer higher quantities of power wirelessly to deep-tissue catheter implants in a cost-effective manner would prove very useful in medicine. This work presents a backscatter-based energy transfer and tracking system for future deep-tissue implants. To transfer power, an open-top ultrasonic transducer would be placed near the skin, the ultrasonic wave can power circuits on the tip of the catheter inside the patient. For the tracking system, transducers use ultrasonic backscattering and time-of-arrival to precisely locate the tip of the catheter. To show this concept will work in future applications, the two major components of the system were tested and validated using commercial off-the-shelf devices with air as medium. We were able to show a one-way 0.34mm localization resolution and track an object in two dimensions with 6.32mm accuracy on the x-axis and 4.27mm on the y-axis. Ultrasonic Wireless Power Transfer (WPT) was modeled using a linear rectangular array approximation via an open-source MATLAB Toolbox known as k-Wave. The developed array model was experimentally validated at distances from 11mm to 310mm using a linear rectangular array approximation of commercially available transducers for transfer efficiencies through air of up to 81.9 percent.

Next generation 5G standards operating at sub-6GHz and millimeter-wave frequencies place stringent requirements on the design of analog-to-digital converters (ADCs) via conversion speed, ENOB, and power consumption. The reduction of supply voltages through increasingly scaled CMOS process nodes further complicates the design process of these circuits. This work presents a 1GS/s sampling based voltage-to-time converter (VTC) in 65nm process with full 2Vpk-pk,diffinput range at only 1mW power consumption. We propose a method for tunable distortion compensation across corners to realize a truly robust design. The proposed design has a low frequency figure-of-merit (FOM) of 3.8 fj/conv-step and a high frequency FOM of 2.46 fj/conv-step. The performance of VTC enables realization of time-to-digital converters (TDC) with high resolutions.

On-chip integrated oscillators are highly needed for the next-generation low-cost sensors used in IoT/biomedical applications to realize sub-millimeter-sized packages at ultra-low-power and fast startup. This paper presents a 25.6μW phase-locked relaxation oscillator (PLL-ROSC) with 8.972ps period jitter using an energy-efficient PLL. A self-locking mechanism is proposed that tracks the temperature variation from -20 to 100°C A current-reuse differential ROSC with boosted output swing is employed to improve noise performance and reduce the power consumption. The simulated power consumption is 15x better than state-of-art with -237.2dBc/Hz FoM and <; 1μs startup time using 180nm CMOS technology.

The performance of traditional compressive sensing (CS) architectures has been tempered by dynamically changing real-world data. This paper demonstrates an information-aware compressive sensing (CS) architecture for dynamic artifact detection of biophysiological signals in wearable applications. Artifacts such as long pause, baseline wandering, and saturation often corrupt recorded data due to environmental factors. In wearable applications where power conservation and ultra-low power operation are paramount, this can lead to wasted power. By combining earlier proposed CS based architectures with an efficient analog feature-extraction (FE) and digital decision making, the sampling rate of the ADC and the integration window of the multiplying DAC can be reduced in presence of artifacts to save power. As shown, this technique can reduce the system power consumption by up to 70% in the more extreme cases of signal corruption. A serialized Walsh-Hadamard Transform (WHT) used for FE is proposed that dramatically simplifies the circuit implementation while the digital classifier comprising of quadratic Support Vector Machine (SVM) classifier ensures low power operation with accurate decision outcomes.

Analog-to-Digital Converts (ADC) are becoming essential to the function of ultra-high speed interconnects (IO) with complex modulation schemes, while at the same time reduction in supply voltage has negatively impacted the performance of such circuits. However the improvement in delay times and reduction in logic size has made time-based ADCs attractive. To accomplish this, a Voltage-to-Time Converter (VTC) is used as the first stage in a two-step conversion process. The performance of the VTC subsequently limits the overall performance of the ADC. This work presents a sampling-based VTC in 65nm CMOS with an input range of +/-0.5V achieving an ENOB of 7.6 bits at 4GS/s up to the Nyquist frequency with overall power of 8 mW only. Resulting output range of +/-63ps allows existing Time-to-Digital Converter (TDC) designs to realize close to this level of performance efficiently when combined to create a analog-time-digital converter (ATDC).

Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two well-known limitations: slow convergence and increased computational complexity/power dissipation for higher adaptive filter orders and sampling frequencies. Half (fs/2) and quarter-rate (fs/4) LMS calibration for oversampled A/D decimators are used to reduce the computational complexity. Noble identities and polyphase decimation are used to implement these schemes to match digital noise-cancellation filters (NCF) to the corresponding transfer functions of an analog fourth-order cascade sigma-delta (ΣΔ) ADC. Energy savings up to 30% compared to conventional full-rate (fs) schemes are confirmed using an Altera Stratix II field programmable gate array (FPGA). The analog front-end comprises a switched-capacitor 2-2 cascade ΣΔ ADC implemented in 0.13 μm CMOS. Using differential-pair opamps with gains of only 22 db and an oversampling ratio OSR = 8, the ΣΔ ADC system achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.

Wireless local area network (WLAN) transmissions in the 5-6 GHz band pose severe desensitization problems for UWB receivers. This paper describes a concurrent Mode-I (3.17-4.75 GHz) and Mode-III (6.34-7.92 GHz) UWB low-noise amplifier (LNA) employing a wideband filter with a tunable notch that attenuates WLAN blockers. Specifically, the notch attenuation and gain are tunable over a wide range. The gain is enhanced using wideband feedback and is programmable from 9-14.5 dB. Simultaneously, blocker attenuation of 10-20 dB over the WLAN frequency band is achieved. Implemented in a 0.13-μm CMOS process and operated with 4.8 mA bias current, the LNA achieves a NF of 4.3-5.1 dB and a minimum IIP3 of -1.1 dBm.

Approaches for modeling continuous-time (CT) SigmaDelta modulators based on the Bilinear (BT), Lossless-Discrete Integration (LDI) and Impulse Invariant (II) transformations are compared for low-OSR cascade architectures. A hybrid modeling approach is introduced that combines the BT and LDI transformations, and enables direct synthesis of the CT modulator from a discrete-time (DT) template. The resulting CT architecture is identical to the DT counterpart; i.e., no new signal paths are introduced. Moreover, frequency warping is not required as in the BT case for low-OSR modulators.

A new sigma-delta architecture employs feed-forward topology with digital summing. The feed-forward architecture reduces the signal swings of the integrators and hence modulator distortion while digital summing eliminates the need for a summing op-amp and makes the design more robust to comparator offsets. Applying this architecture to a 2-2 cascade ADC, we can achieve a 12b resolution over a 10MHz signal bandwidth with a sampling rate of 160 MSamples/sec. The topology is especially attractive for low-power and low-voltage applications.