Digital magnitude comparators are used in digital systems to compare two binary numbers and to determine if the numbers are equal, or if one number is greater or less than the other. In this work the design of magnitude comparators in dynamic logic is examined. Two dynamic logic magnitude comparator designs are proposed and compared. One of these designs exploits an existing simplification, while the other is a totally new one. The new dynamic logic comparator design compared over the one based on the existing simplification, shows less hardware complexity, consumes less power and has lower power delay-product, for typical operand widths.

The 2's complement representation is widely adopted, since compared to the other signed number systems has the advantage of simpler addition and single representation of zero. Sing-magnitude representation is used in digital signal processors for the representation of digital signals for low-power purposes. The 1's complement representation compared to the 2's complement one has the advantages of the simpler conversion to and from the sign-magnitude representation, simpler negation and that truncation of negative numbers is equivalent to that of the sign-magnitude representation. Therefore, the design of efficient arithmetic units for this system should be examined. In this work 1's complement modified Booth multipliers with complexity similar to that of the 2's complement ones are proposed.

Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM-like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff.

International Data Encryption Algorithm (IDEA) is a popular and secure cryptography algorithm, suitable for hardware implementation. IDEA comprises of modulo 216 additions, bitwise exclusive-OR operations and modulo 216+1 multiplications of 16-bit words. Among them, modulo 216+1 multiplication is the most time, space and power consuming operation. In this work, we propose an efficient modulo 2n+1 modified Booth multiplication algorithm which is adapted to operands used in the IDEA. The IDEA multiplier based on the proposed modulo 2n+1 multiplication algorithm yields area and power advantages of up to 12% and 14% respectively, compared to the already proposed modulo 2n+1 multiplier designs. The implementation of a single round of the IDEA block cipher based on the proposed multiplier verifies the area and power advantages over the implementations based on existing modulo 2n+1 multipliers.

Input vector monitoring concurrent BIST schemes perform testing concurrently with the operation of the circuit. In this work a novel input vector monitoring concurrent BIST scheme is presented that compares favorably to previously proposed schemes with respect to the required hardware overhead.

In this paper, we propose an efficient residue generator which concurrently computes the residues modulo 2n+1 and modulo 2n-1. The input operands are divided into n-bit vectors which are then grouped into two sets and added by two separate Carry Save Adder (CSA) trees. The output carry of each stage of the first CSA tree is used as input to the corresponding stage of the second CSA tree, while the output vectors of the trees are finally added modulo 2n+1 and 2n-1 to compute the residues. The proposed residue generator is well suited for Residue Number System (RNS) based applications which use both modulo 2n+1 and 2n-1 residues. An efficient configurable modulo 2n±1 residue generator is also proposed.

In this work new efficient modulo 2n+1 residue generators are proposed. The input operands are divided into n-bit vectors which are added by an inverted end around carry save adder tree and a final stage diminished-1 modulo 2n+1 adder. The conversion of the proposed residue generators to configurable modulo 2n±1 ones is also discussed. Modulo 2n±1 residue generators find applicability as forward converts from the binary to the residue number system, and in the design of self-checking digital systems.

In this work a new efficient modulo 2n+1 modified Booth multiplication algorithm for operands in the weighted representation is proposed. According to our algorithm [n/2]+2 partial products are derived. The resulting partial products are reduced by an inverted end around carry save adder tree to two operands, which are finally added by a diminished-1 modulo 2n+1 adder. Our design compares favorably for both area and delay to the modulo 2n+1 modified Booth multipliers previously proposed.

Input vector monitoring concurrent Built-In Self-Test (BIST) schemes can circumvent problems appearing separately in on-line and off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required in order to complete the concurrent test. In this paper a novel input vector monitoring concurrent BIST scheme is presented. The proposed BIST scheme is shown to have lower hardware overhead for the same values of the concurrent test latency compared to previously proposed schemes.

In this paper a high-speed cryptographic coprocessor, named HSSec, is presented. The core embeds two hash functions, SHA-1 and SHA-512, and the symmetric block cipher AES. The architecture of HSSec renders it suitable for widely spread applications with security demands. The presented co-processor can be used in every system integrating standards such as IPSec or the upcoming JPSec and P1619. The main characteristic of the proposed implementation is common use of the available resources, to minimize further area requirements. Additionally the cryptographic primitives can operate in parallel, providing high throughput whenever needed. Finally the system can operate in ECB or CBC modes. The HSSec co-processor has relatively small area and its performance reaches 1 Gbps (AES, SHA-1 and SHA-512) for XILINX's Virtex II FPGA family.

Domino CMOS circuits are an option for speeding up critical units. An inherent problem of Domino logic is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of a circuit can violate the noise margins and cause erroneous responses at the output. The dominant solution to this problem is the multiple precharging of the gate's internal nodes. However, the added precharge transistors are not testable for stuck-open faults. Undetectable stuck-open faults at these transistors may cause noise margins reduction and consequently may affect the reliability of the circuit since its operation in the field will be sensitive to environmental factors such as noise. In this paper, we propose new multiple precharging design schemes that enhance Domino circuits' testability with respect to transistor stuck-open and stuck-on faults

A new modulo 2n+1 multiplier architecture is proposed for operands in the normal representation. The novel architecture is derived by showing that all required correction factors can be merged into a single constant one and by treating this, partly as a partial product and partly by the final parallel adder. The proposed architecture utilizes a total of (n+1) partial products, each n bits wide and is built using an inverted end-around-carry, carry-save adder tree and a final parallel adder.

In this work, we propose a new algorithm for designing diminished-1 modulo 2/sup n/+1multipliers. The implementation of the proposed algorithm requires n + 3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2/sup n/+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations.

Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2/sup n/ + 1. To avoid using (n + 1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2/sup n/ + 1 arithmetic applications. In this paper, for the first time in the open literature, we formally derive modulo 2/sup n/ + 1 squarers that adopt the diminished-1 number system. The resulting implementations are built using only full- or half-adders and a final diminished-1 adder and can therefore be pipelined straightforwardly.

2/sup n/-1 is one of the most commonly used moduli in residue number systems. In this paper, we propose a new method for designing modified Booth modulo 2/sup n/-1 multipliers, which, for even values of n, require one less partial product than the already known. CMOS implementations reveal that the proposed multipliers compared to earlier solutions offer savings up to 28.7 percent and up to 29.3 percent in the implementation area and execution delay, respectively.

Modulo 2/sup n/+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2/sup n/+1 adders, based on parallel-prefix carry computation units, the first architecture utilizes a fast carry increment stage, whereas the second is a totally parallel-prefix solution. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implementation area and execution latency.

We reveal the cyclic nature of idempotency in the case of modulo 2/sup n/-1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2/sup n/-1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.

In this paper we present a new pseudorandom BIST scheme for high-speed adders. Under this scheme an adder is simultaneously used as a test pattern generator and as a response compactor during its own testing. The main advantages of the proposed scheme, compared to prior methods, are minimal performance penalty, small hardware overhead and the benefits of at-speed testing.

We present new design methods for modulo 2/sup n//spl plusmn/1 adders. We use the same select-prefix addition block for both modulo 2/sup n/-1 and diminished-one modulo 2/sup n/+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.

Modulo 2/sup n/ -1 adders as fast as n-bit 2's complement adders have been recently proposed in the open literature. This makes a residue number system (RNS) adder with channels based on the moduli 2/sup n/, 2/sup n/ - 1, and any other of the form 2/sup k/ - 1, with k < n, faster than RNS adders based on other moduli. We formally derive a parametric, with respect to the adder size, test set, for parallel testing of the channels of an RNS adder based on moduli of the form 2/sup n/, 2/sup n/ - 1, 2/sup k/ - 1, 2/sup l/ - 1, ..., with l < k < n. The derived test set is reusable; it can be used for any value of n, k, l, ..., regardless of the implementation library used and is composed of n/sup 2/ + 2 test vectors. A test-per-clock BIST scheme is also proposed that applies the derived test vectors within n/sup 2/ + 2n cycles. Static CMOS implementations reveal that the proposed BIST offers 100 percent postcompaction fault coverage and an attractive combination of test time and implementation area compared to ROM and FSM-based deterministic BIST or LFSR-based pseudorandom BIST.

This paper presents two new design methodologies for modulo 2/sup n/+1 addition in the diminished-one number system. The first design methodology leads to carry look-ahead, whereas the second to parallel-prefix adder implementations. VLSI realizations of the proposed circuits in a standard-cell technology are utilized for quantitative comparisons against the existing solutions. Our results indicate that the proposed carry look-ahead adders are area and time efficient for small values of n, while for the rest values of n the proposed parallel-prefix adders are considerably faster than any other already known in the open literature.

We present a new methodology for designing modulo 2/sup n/+1 adders with operands in the diminished-one number system. The proposed methodology leads to parallel-prefix adder implementations. Both an analytical model and VLSI implementations in a standard-cell technology are utilized for comparing the adders designed following the proposed methodology against the existing solutions. Our results indicate; that the proposed parallel-prefix adders are considerably faster than any other already known in the open literature and as fast as the corresponding modulo 2/sup n/ and modulo 2/sup n/-1 adders.

A novel parallel-prefix architecture for high speed module 2/sup n/-1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallel-prefix or carry look-ahead structures.

A design method for a combinational totally self-checking (TSC) 1-out-of-3 code checker is presented. This method is not only simpler and more efficient than others, but is also successful in the case where more than one 1-out-of-3 code exists in a TSC system.>