Ching-Yuan Wu

dblp:11/6954 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › technology computer-aided design
device simulation
0.021993
A new grid-generation method for 2-D simulation of devices with nonplanar semiconductor surface · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
A new methodology for two-dimensional numerical simulation of semiconductor devices · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation › technology computer-aided design
semiconductor device simulation
0.021993
A new grid-generation method for 2-D simulation of devices with nonplanar semiconductor surface · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
A new methodology for two-dimensional numerical simulation of semiconductor devices · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992
Electronic design automation
mesh generation
0.011993
A new grid-generation method for 2-D simulation of devices with nonplanar semiconductor surface · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Electronic design automation › technology computer-aided design › device simulation
numerical device simulation
0.011992
A new methodology for two-dimensional numerical simulation of semiconductor devices · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1992

Methods — techniques the papers use, named apart from their topics

jacobian iteration · 0.0fourier series · 0.0fast fourier transform · 0.0conformal mapping · 0.0green's function method · 0.0finite difference discretization · 0.0SLOR nonlinear iteration · 0.0
YearPublicationVenuePosition
1993 A new grid-generation method for 2-D simulation of devices with nonplanar semiconductor surface
abstract
A general analytical method is proposed for transforming a 2-D multilayer physical domain with the nonplanar semiconductor surface into a 2-D rectangular mathematical domain with a planar surface, with a set of Fourier series being used to describe a general conformal mapping for each layer. Based on the method, a simple iteration algorithm, which incorporates a nonlinear Jacobian-iteration method with the fast Fourier transform (FFT), is developed to solve the system of nonlinear equations due to the mutually coupled boundary conditions. As a result of the analytical conformal mapping, a regular, deformable grid structure can be applied to simulate the device structure with the nonplanar semiconductor surface, and the device simulator using the conventional rectangle-based grid can be easily modified to simulate the device with the nonplanar semiconductor surface.>
Shan-Ping Chin, Ching-Yuan Wu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1992 A new methodology for two-dimensional numerical simulation of semiconductor devices
abstract
A methodology for obtaining the self-consistent solution of semiconductor device equations discretized in the finite-difference scheme is proposed, in which a new discretized Green's function solution method is used to solve the two-dimensional discretized Poisson equation and a surface mapping technique is developed to treat arbitrary surface boundary conditions. The two-dimensional potential distribution can then be expressed in terms of charge density distribution and bias conditions. Using the derived potential distribution, the SLOR-nonlinear iteration for the current continuity equations of both carriers can be performed by incorporating a new algorithm to obtain the self-consistent solution of a full set of semiconductor device equations without any outer iteration. An Si MESFET simulation demonstrates that the convergent rate of the proposed method can be speeded up to 4-8 times that of Gummel's method. The new method can be incorporated with the conventional solution methods to get a stable and efficient computation scheme.>
Shan-Ping Chin, Ching-Yuan Wu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2