Demo Data from EDBT 2026 / reviewers in the wild / expert
Thomas F. Fox
dblp:11/6997
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Processor architecture and microarchitecture · 55% Integrated circuit design · 15% Electronic design automation · 15% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
microprocessor design |
0.0 | 1 | 1994 | The Design of High-Performance Microprocessors at Digital · DAC 1994 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1994 | The Design of High-Performance Microprocessors at Digital · DAC 1994 |
Processor architecture and microarchitecture
instruction-level parallelism |
0.0 | 1 | 1976 | Scheduling Parallel Processable Tasks for a Uniprocessor · IEEE Trans. Computers 1976 |
Parallel and multicore computing
parallel programming models |
0.0 | 1 | 1976 | Scheduling Parallel Processable Tasks for a Uniprocessor · IEEE Trans. Computers 1976 |
Parallel and multicore computing
task scheduling |
0.0 | 1 | 1976 | Scheduling Parallel Processable Tasks for a Uniprocessor · IEEE Trans. Computers 1976 |
Embedded and real-time systems › real-time scheduling
uniprocessor scheduling |
0.0 | 1 | 1976 | Scheduling Parallel Processable Tasks for a Uniprocessor · IEEE Trans. Computers 1976 |
Embedded and real-time systems
real-time scheduling |
0.0 | 1 | 1976 | Scheduling Parallel Processable Tasks for a Uniprocessor · IEEE Trans. Computers 1976 |
Methods — techniques the papers use, named apart from their topics
processor-i/o overlap · 0.0multi-programming · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | The Design of High-Performance Microprocessors at Digitalabstractmicroprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's microprocessor designers strive for global optimizations across the design space, develop innovative highspeed custom circuit design techniques, and use state-of-the-art manufacturing technology for fabrication. With microprocessor performance increasing at a rate of 50 % per year, quick time-to-market is crucial. Logic and circuit bugs that would prevent first-pass silicon from booting the operating system must be eliminated before tape out if unacceptable schedules delays are to be avoided. Quick time-to-market is achieved by: fostering good design practice through the use of a consistent methodology and detailed design reviews; accounting for manufacturing variations and long-term reliability concerns from the start of the design; and subjecting the chip models to rigorous logical and electrical verification prior to prototype fabrication. This paper presents a practical view of Digital's design process. I. Thomas F. Fox |
DAC | 1 |
| 1976 | Scheduling Parallel Processable Tasks for a UniprocessorabstractRecent advances in multiprogramming have been concentrated on multiprocessor systems. But overlap in operations is also permissible in uniprocessor systems in which the processor instruction execution and input–output operations are handled by separate units. By maximizing the processor and input–output overlap, a program can be executed faster while the system utilization is highly improved. C. V. Ramamoorthy, Thomas F. Fox, Hon Fung Li |
IEEE Trans. Computers | 2 |