This paper presents a 13-tap FIR filter and an IIR filter embedded in a 10-bit SAR ADC for wireless communications chip. The IIR filter can be inherently realized through reusing the capacitor array of the SAR ADC, thus improving the stopband suppression and shaping the transition band. Besides, the DC attenuation is also avoided. The sampling rate loss of the SAR ADC can be compensated by the$4\times $time-interleaving technology. The proposed filter features high power-efficient, linearity and process compatibility. Compared with a 15-tap FIR filter, the out-of-band suppression at the cut-off frequency (OOBS@$f_{\mathrm {cut-off}}$) is enhanced by 9dB theoretically. A prototype FIR/IIR filter in 40nm CMOS occupies an active area of 0.067mm2, consumes$38~\mu \text{W}$at a single supply of 1.1V, has a 1-MHz bandwidth, obtains$>$42.2dB [email protected] when operated at 40MS/s. Meanwhile, the SAR ADC without/with the proposed filter can achieve a FoMw of 7.91 fJ/conversion-step and 13.5 fJ/conversion-step, respectively.

This article presents a “three unary bits +five splitting bits + four binary bits” segmented 500-MS/s current-steering digital-to-analog converter (DAC). The proposed splitting decoding method is between the unary decoding and binary decoding, in terms of number of switched elements. It can optimize the differential nonlinearity and output glitches of DAC, with a more simplified circuit scale than unary decoding method. Due to the data-transmission topology, both the proposed thermometer and splitting decoders feature lower transistor count and occupy less area than other competitors. Their low latency accommodates to fast synchronization control of current source switches and its beneficial to the spurious-free dynamic range (SFDR) improvement of DAC. When implemented in a 0.18-$\mu \text{m}$CMOS process, the 12-bit DAC occupies an active area of 536$\mu \text{m}\,\,\times \,\,340\,\,\mu \text{m}$, with the proposed decoders occupying only 28$\mu \text{m}\,\,\times \,\,75\,\,\mu \text{m}$. The DAC dissipates 17.20 mW at 500 MS/s with a 1.8-V analog supply and a 1.2-V digital supply. The differential and integral nonlinearities are measured to be 0.28 and 1.16 LSB, respectively. The DAC also features SFDRs of 68.83 and 62.06 dB for input signals of 6.34 and 239.74 MHz, respectively.

A generic statistical model for calculating input-referred noise of an analog-to-digital converter (ADC) impaired by thermal noise is proposed. Based on this model, detailed statistical analyses are performed on three successive approximation register (SAR) ADCs and the analytical results obtained are verified with Monte Carlo simulations. To compare the input-referred noise of different SAR ADC architectures, a noise gain factor is proposed, which relates the noise at the comparator input (top plate of capacitor array) to that at the ADC input. The noise gain factors are computed and compared for all three ADCs analyzed. The model and methodology presented in this paper can be applied to various ADC architectures for circuit design and optimization.