Permanent Magnet Synchronous Motors (PMSMs) are widely used in electric vehicles, manufacturing systems, and renewable energy applications, where system reliability is vital for performance and safety. This paper proposes an intelligent condition monitoring framework that integrates Continuous Wavelet Transform (CWT) with Deep Transfer Learning (DTL) using a pretrained GoogLeNet 2 dimensional Convolutional Neural Network (2D-CNN) for advanced diagnosis of common PMSM faults. The method converts d-axis and q-axis voltage signals into high-resolution CWT scalograms, enabling rich time–frequency feature representation of motor behaviour under both healthy and faulty conditions. These spectrograms are used to fine-tune only the final layers of GoogLeNet, significantly reducing training time and computational complexity compared to training from scratch. Moreover, since TL requires far less labelled data, it reduces the cost of data acquisition—which is often expensive and time-consuming in industrial settings. The proposed framework demonstrates strong adaptability across fault types, achieving high classification accuracy with 100%, 98.6%, 96.6%, and 100% for healthy, partial demagnetisation, static rotor eccentricity, and inter-turn short circuit (ITSC) respectively. By combining pretrained CNNs with wavelet-based voltage imaging, this approach delivers an efficient, cost-effective, and scalable solution for PMSM condition monitoring in complex operational environments.

In this paper, we present a fully integrated ring-oscillator (RO)-based temperature sensor for quantum computing applications. As the quantum states exhibit an exponential sensitivity to the on-die cryogenic temperature change, any such temperature variation due to, for example, local heating islands arising from the poor thermal conductivity of silicon should be monitored. For this purpose, we exploit a compact RO sensor placed in the vicinity of qubits. The proposed approach employs four differently sized oscillators and two VBGs to generate, in total, eight different temperature-dependent oscillating frequency signals. Then, by performing their polynomial fitting, a linear temperature-frequency compensating model for the proposed sensor is derived. Fabricated in 22 nm FD-SOI technology, the proposed sensor occupies 0.0016 mm2, consumes 128 μW and achieves maximum inaccuracy of ± 2.1 K in a wide temperature range from 3 to 270 K.

In this paper, we present an inverter-based ring oscillator (RO) operating at cryogenic temperatures for quantum computing applications. It employs a low-dropout regulator (LDO) to provide supply voltage for a programmable switched-capacitor system which isolates the supply line of the integrated RO circuit from any noise or perturbations of the external power supply. In anticipation of embedding the RO into a phase-locked loop (PLL), we study the variation of flicker phase noise from cryo to room temperature by indirectly measuring the phase noise (PN) in the 30dB/dec region. The proposed system occupies 0.012mm2and shows 3.5dB integrated PN improvement thanks to the proposed voltage supply noise reduction technique at room temperature (RT) and the FOM is estimated as 121.7dB at cryogenic temperature (CT).

Quantum computers promise to revolutionize information processing, offering game-changing opportunities in fields such as cryptography, machine learning, drug discovery, etc. However, building large-scale quantum computers presents significant challenges, requiring both fundamental research and technological breakthroughs. Among the various platforms proposed for the realization of the core of the quantum hardware, qubits realized in semiconductor nanostructures stand out. One of their key advantages lies in their compatibility with standard semiconductor manufacturing, enabling, among other capabilities, their co-integration with control and readout electronics, thus improving scalability and reducing interconnect complexity. In this review, we discuss recent advances in silicon-based spin qubits and present an overview of the progress and challenges in developing large-scale quantum computing systems based on this architecture.

In this paper, we present the characterisation of ring oscillator (RO) test circuits fabricated in GlobalFoundries’ (GF) 22nm fully depleted silicon-on-insulator (FD-SOI) process and operating from 200 K down to 4 K. We investigate ROs using NAND, NOR, and inverter standard cell libraries, including low, regular, and high threshold-voltage versions. Alongside temperature variations, we also consider a change in the power supply of ±5% from a nominal 0.8 V. The ROs demonstrate the combined effect of increased mobility, increased threshold voltage, and leakage current processes at cryogenic temperatures on their operation. By averaging over 81 fabricated ROs using three different delay gates and 2 different flavours, we report a statistical characterisation of their properties in the FD-SOI technology over temperature and supply voltage.

We propose a simplified and efficient apparatus for a cosmic microwave background (CMB) detector employing a cryogenic controller IC for a large TES (Transition Edge Sensor) array. The proposed apparatus significantly improves the passive heat load by reducing the number of wires originating from the room temperature electronics. In the current proposal, the cryogenic controller handles two critical circuit functions, namely the row multiplexer and the bias DAC. Those circuits can be scaled to handle a large number of channels required for the next generation of CMB telescopes with 500 k detectors. As a step towards realizing such a solution, the aforementioned circuits are designed using a low power and low noise topology and simulated to verify system specification compliance. The circuit design is fabricated in Global-Foundries 22-nm FD-SOI CMOS process and is awaiting lab measurements.

This paper proposes the use of a tunable$LC$resonator to read an array of qubits in a multiplexed fashion, by making the dispersive shift of the targeted qubit dominant. Cavity and circuit electrodynamics (QED) theory is shown to support this idea. The tunable capacitor array, in parallel with a superconducting inductance, is designed to maximize the quality factor by frequency range product,$Q\cdot\Delta\omega$. This approach only requires one RF signal to measure multiple qubits, which can facilitate quantum computing scaling.

In this paper we demonstrate electrostatic control and feasibility of entanglement in CMOS qubits. We present both single particle and multi-particle methodologies to describe quantum transport using a time-dependent Hamiltonian assuming one spatial degree of freedom. The developed models predict maximally entangled states of electrons controlled electrostatically by external driving fields and interacting via the Coulomb force.

We describe a quantum computing hardware paradigm that exploits the current scaling achievements of mainstream CMOS technology. Just like in a small IC chip, where a single nanometer-sized CMOS transistor can be reliably replicated millions of times to build a digital processor, we propose a new structure of a qubit realized as a CMOS-compatible charge-based quantum dot that can be reliably replicated thousands (or perhaps even millions) of times to construct a quantum processor. Combined with an on-chip CMOS controller, it will realize a useful quantum computer (QC) that can operate at 4 K, which is much higher than the temperature of today's QCs of 15 mK.

A novel built-in calibration mechanism for a nonlinear digitally-controlled power amplifier (DPA), or its combination with an external power amplifier (PA), is proposed. It allows construction of a digital predistortion mechanism, which is configured based on data collected entirely through processing of internal digital signals in an all-digital PLL (ADPLL)-based transmitter. The proposed technique is suitable not only for characterizing the amplitude and phase transfer function non- linearities and configuring the internal predistortion accordingly, but may also be useful for built-in self-test (BIST) purposes. The proposed technique has been implemented and successfully validated in a commercial single-chip GSM/EDGE radio.