At some point in the future, the majority of vehicles will be autonomous. When exactly that time will be, depends not only on technical availability but also on social acceptance. Confidence in such a technical system plays an essential, if not decisive, role. Already today, automotive semiconductors have high safety requirements as well as stricter quality and reliability targets than semiconductors supplied for consumer markets. This presentation will shed light on the challenges on the hardware side in the realization of semiconductor components for autonomous vehicles. The requirements on safety and reliability for the car of the future will increase. The measures already used today during manufacturing test, for Design-for-Test and for safety enablement need to be supplemented or replaced.

The significant process parameter variations occurring during fabrication of high performance sequential circuits, such as microprocessors, are posing relevant uncertainties on the power that such circuits will consume in the field, while executing workloads typical for the diverse products they are oriented to (e.g., cellular phones, notebooks, servers, etc). On the other hand, different kinds of products have different constraints on the maximal power that could be consumed during the execution of typical workloads, due to diverse needs in terms of charge autonomy, heat dissipation, etc. Consequently, the power that will be consumed by microprocessors during the execution of typical workloads in the field needs to be accurately characterized at the end of fabrication. Such a power consumption characterization (hereinafter referred to as “power binning”), will enable to classify microprocessors in “power bins”, each one containing microprocessors suitable for different kinds of products, thus enabling to introduce them all into the market for different kinds of products. Based on these considerations, in this paper we propose an approach to characterize accurately at the end of fabrication, and at low-cost (in terms of characterization time), the power that microprocessors will consume in the in-field during the execution of workloads typical for different kinds of products. Our approach exploits scan-based Logic Built-In Self-Test (LBIST) to apply to microprocessors' sequential blocks test vectors that induce on their internal nodes an activity factor (AF) similar to that experienced during the in-field execution of workloads typical for different kinds of products, thus enabling to perform power binning by simply measuring their consumed power. Our approach enables to scale the AF from 0 percent up to 97.6 percent (on average for the considered benchmark circuits) compared to conventional LBIST, with a granularity of the 2 percent, thus enabling to emulate accurately the AF induced by workloads typical of a wide range of products. We propose a hardware implementation for our approach requiring a limited area overhead (lower than 3 percent) over conventional LBIST.

In a high-volume manufacturing environment, it is difficult to set up test conditions, including supply-voltage levels, that can take into account the wide range of interdie process variations on a wafer. Test conditions that do not take into consideration these process variations can lead to either yield loss or poor quality control. In this work, we propose a method to identify supply-voltage levels to test semiconductor chips based on the process variations experienced by them, while also adapting these supply-voltage levels based on the chip locations on the wafer. For this purpose, we first identified various process zones on the wafer, based on frequencies of on-chip ring oscillators. Next we modeled the ring oscillator (RO) performance in terms of the variations in SPICE parameters using the design of experiments (DoE) method. The equation corresponding to the DoE model was solved for each process zone on the wafer in order to fit a set of independent SPICE parameters set for the corresponding zone. These independent SPICE parameters were then used to create an updated SPICE model for the ring oscillator corresponding to each zone, and these SPICE models were used to derive an appropriate supply-voltage level for each zone. The results were used to test 250 devices to identify chips that exhibit significant performance deviation compared to other chips from the same zone. Among these 250 devices, 89 belonged to the slow zone, 87 belonged to the medium-fast zone, and 74 belonged to the fast process zone. A total of seven devices from the medium-fast zone and nine devices from the fast zone showed performance deviations and they were successfully screened.

Thermal phenomena occurring along test execution at the final stages of the manufacturing flow are considered as a significant issue for several reasons, including dramatic effects like circuit damage that is leading to yield loss. This paper tries to redeem those bad guys in order to exploit them to improve the test quality, reducing the overall test cost without affecting the yield.

Production test is a significant driver of semiconductor manufacturing cost. Test cost is highly influenced by the test concept of a product. This paper gives an overview over the test concept of a complex mobile phone SOC. The particular example is a highly integrated SOC for entry-level mobile phones. The SOC consists, besides digital processing units, of a variety of embedded M/S blocks, an embedded FM radio, and a complete RF transceiver for mobile communication. The paper describes the production test approaches for different groups of embedded circuitry, e.g. digital logic, mixed-signal, etc. Design-for-Test measures are briefly described. A breakdown of relative test times, proportional to production test cost, with respect to different groups of circuitry is presented. Limitations of existing test equipment and future challenges in order to further reduce test cost for complex SOCs are explained based on industrial implementation experience.