With shrinking device geometries, the device-to-device (D2D) variability of emerging memory devices, affect the performance of deep neural networks (DNN) and restrict the use of standalone devices to be used as Analog in-Memory Computing (AiMC) accelerators. For FeFET based AiMC designs, such effects can be controlled by using resistors or capacitors connected in series with FeFETs. However, in both cases, the effect of variability will again start dominating when the programming window shrinks further due to scaling towards smaller nanometer dimensions. Additionally, while resistance based solutions will add to the existing IR drop issues within the macro, capacitor based approach avoids such a case. In this paper, we evaluate a FeFET and capacitor based AiMC accelerator and study how finetuning cell operating parameters along with design modifications of the AiMC macro, can help in achieving a variability aware AiMC design. Using a 22-nm CMOS PDK augmented with FeFET model based on measured data, evaluation on a DNN with CIFAR-10 benchmark, demonstrated that following our approach, the implemented DNN achieves an accuracy of ∼85% which is an improvement of ∼13% over an untuned AiMC macro.

The high-injection MOS (HIMOS) technology was initially developed as an application-specific memory technology, i.e., a nonvolatile block-erasable (Flash-type) memory for embedded applications. The label "embedded" points out that cost was considered to be the prime issue. Because of this, processing complexity and voltage reduction have been the major driving forces in the cell and process development rather than mere cell size scaling. Indeed, what really counts in embedded applications is the chip area per megabit rather than the cell size itself. Because the substantially high operating voltages of floating-gate-based memories are not being scaled, the peripheral area becomes the main bottleneck for most embedded applications. Also, cost has to be viewed in terms of masking steps and complexity or marginality of processing in general, especially in the case of embedded Flash, since the envisaged products have to be incorporated in a conventional CMOS line. To achieve this goal, a split-gate approach was adopted, which, combined with an additional program gate (PG), leads to maximized hot-electron efficiency at low voltages. As an additional major advantage, this PG allows the use of an electrically erasable programmable ROM-like threshold voltage window. This implies that the high threshold needs to be only slightly positive, while the low one could be strongly negative. Such a scheme allows very low excess charge levels (especially in the more critical off state), which greatly improves device reliability, while allowing further scaling of the tunnel oxide as compared with other Flash concepts. This allows further reduction of the program/erase voltages. Also, such a window provides a larger read current, which removes the necessity for wordline boosting during readout and therefore improves access time.