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Harshit Agarwal

dblp:115/6346 · DBLP profile ↗
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8ranked-venue papers
0as first author
2since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 since 2021Computer networks · 3Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 68% Electronic design automation · 32%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › semiconductor device modeling
compact modeling
0.922023
Robust Compact Model of High-Voltage MOSFET's Drift Region · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Electronic design automation › technology computer-aided design
device simulation
0.712023
Robust Compact Model of High-Voltage MOSFET's Drift Region · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Integrated circuit design
analog and mixed-signal circuits
0.422023
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Robust Compact Model of High-Voltage MOSFET's Drift Region · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Integrated circuit design › semiconductor device modeling
transistor modeling
0.212015
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015
Electronic design automation
circuit simulation
0.112015
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2015

Methods — techniques the papers use, named apart from their topics

voltage-dependent formulation · 0.7SPICE simulation · 0.7compact modeling · 0.2
YearPublicationVenuePosition
2026 Efficient and Secure Lattice-Based Unique Ring Signature with Applications in IoT
Vishal Pareek, Chinmoy Biswas, Harshit Agarwal, Aditi Kar Gangopadhyay, Sugata Gangopadhyay
J. Supercomput.3
2023 Robust Compact Model of High-Voltage MOSFET's Drift Region
abstract
This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and behavioral issues that can arise in SPICE simulations with the existing current-dependent formulation in Berkeley-Short-Channel-IGFET model (BSIM) for HV transistors. We then demonstrate how a voltage-dependent formulation can mitigate them without losing simplicity and accuracy. We also validate the proposed model against experimental data of HV transistors.
Girish Pahwa, Ravi Goel, Garima Gill, Harshit Agarwal, Yogesh Singh Chauhan, Chenming Hu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5
2015 Modeling STI Edge Parasitic Current for Accurate Circuit Simulations
abstract
We enhance the capability of industry standard compact model BSIM6 to model the parasitic current$ I_{{\text {edge}}}$at the shallow trench isolation edge. Accurate, efficient, and scalable model for$ I_{{\text {edge}}}$is developed by finding the key differences between$ I_{{\text {edge}}}$and main device drain current ($ I_{{\text {main}}}$). It is found that$ I_{{\text {edge}}}$has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to$ I_{{\text {main}}}$. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.
Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chenming Hu
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2014 How does representational competence develop? Explorations using a fully controllable interface and eye-tracking
Aditi Kothiyal, Rwitajit Majumdar, Prajakat Pande, Harshit Agarwal, Ajit Ranka, Sanjay Chandrasekharan
ICCE4
2014 Learning automata-based multi-constrained fault-tolerance approach for effective energy management in smart grid communication network
Sudip Misra, Parimala Venkata Krishna, Vankadara Saritha, Harshit Agarwal, Aditya Ahuja
J. Netw. Comput. Appl.4
2013 A fault-tolerant routing protocol for dynamic autonomous unmanned vehicular networks
abstract
Due to various operational constraints on the unmanned autonomous vehicle (AUxV) networks operating in an adversarial environment, a fault-tolerant routing scheme is an imperative need. Looking at the risk involved in their applications such as search and rescue, threat surveillance, chemical and biohazard sampling, even a fault of minor nature in the system software/hardware may result in destructive consequences. The AUxV network member nodes vary in architecture, capability, application and power of their internal systems. In such a case it is important that the fault-tolerant scheme should take into consideration the kind of heterogeneity involved and should be able to perform in such a scenario as well. Therefore, to address these issues, in this paper we propose a cross-layer and learning automata (LA) based fault-tolerant routing algorithm for AUxVs, named as ULARC (Unmanned Vehicle Network with LA based Routing using Cross Layer Design). We use the theory of LA for the selection of optimal path for routing between source and destination. In this paper, we also focus on making our proposed strategy an energy-efficient one by using a cross-layer architecture for sleep scheduling of nodes. Further, we have devised an α-based scheduling scheme which further adds to the energy efficiency of our protocol by reducing the overhead on the network.
Sudip Misra, Athanasios V. Vasilakos, Mohammad S. Obaidat, Parimala Venkata Krishna, Harshit Agarwal, Vankadara Saritha
ICC5
2013 Learning automata-based virtual backoff algorithm for efficient medium access in vehicular ad hoc networks
Parimala Venkata Krishna, Sudip Misra, Vankadara Saritha, Harshit Agarwal, Naveen K. Chilamkurti
J. Syst. Archit.4
2012 An adaptive learning approach for fault-tolerant routing in Internet of Things
abstract
Internet of Things (IOT) is a wireless ad-hoc network of everyday objects collaborating and cooperating with one other in order to accomplish some shared objectives. The envisioned high degrees of association of humans with IOT nodes require equally high degrees of reliability of the network. In order to render this reliability to IOT networks, it is necessary to make them tolerant to faults. In this paper, we propose mixed cross-layered and learning automata (LA)-based fault-tolerant routing protocol for IOTs, which assures successful delivery of packets even in the presence of faults between a pair of source and destination nodes. As this work concerns IOT, the algorithm designed should be highly scalable and should be able to deliver high degrees of performance in a heterogeneous environment. The LA and cross-layer concepts adopted in the proposed approach endow this flexibility to the algorithm so that the same standard can be used across the network. It dynamically adopts itself to the changing environment and, hence, chooses the optimal action. Since energy is a major concern in IOTs, the algorithm performs energy-aware fault-tolerant routing. To save on energy, all the nodes lying in the unused path are put to sleep. Again this sleep scheduling is dynamic and adaptive. The simulation results of the proposed strategy shows an increase in the overall energy-efficiency of the network and decrease in overhead, as compared to the existing protocols we have considered as benchmarks in this study.
Sudip Misra, Anshima Gupta, Parimala Venkata Krishna, Harshit Agarwal, Mohammad S. Obaidat
WCNC4