This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and current mirror-based paths, are combined to increase the transconductance, thus leading to larger dc gain and higher gain bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells are employed as variable current sources to provide class-AB operation and adaptive biasing of all other drivers. The proposed structure includes several input-to-output paths that play the role of dynamic current boosters during the slewing phase, thus improving the slew rate (SR) performance. The circuit was fabricated in a TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.5\times 30.1\,\,\mu \text{m}$. Experimental results show a GBW of 173.3 MHz, a dc gain of 72.7 dB, and an SR of 139.4 V/$\mu \text{s}$for a capacitive load of$2\times5$pF. The proposed circuit consumes 619$\mu \text{W}$of power, under a supply voltage of 1.8 V.

In this brief, two current generator circuits are used to design a self-biasing transconductance amplifier. The current generators are configured using two n-channel and p-channel cascode current mirrors by which a high input dynamic range is achieved. Since such a topology creates positive feedback, the transconductance of the circuit is also increased causing higher performance. To ensure the stability of the circuit, constant current sources can be paralleled with the current mirror topologies, which of course are implemented using input drivers. Therefore, two n-channel and p-channel input differential pairs are added to the current generator circuits by which not only a rail-to-rail operation is achieved but also the amplifier is stabilized. The proposed circuit was fabricated in the TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.1\times 71\,\,\mu \text{m}$. Under a 1.8-V supply voltage, the experimental results showed a high input common-mode range (ICMR), while a gain bandwidth (GBW) of 83.9 MHz was measured for a capacitive load of$2\times6$pF. In addition, a dc gain and a slew rate (SR) of 68.4 dB and 71.7 V/$\mu \text{s}$, respectively, were achieved.

This work presents a tail-less fully differential bulk-driven transconductance amplifier without using a common-mode feedback (CMFB) circuit. The proposed amplifier employs two P-type and N-type current mirrors to form two self-biasing positive feedback loops resulting in a double transconductance. The bulk terminals of the P-type current mirrors are used as the input nodes to provide a high input dynamic range. The diode-connected topologies of the current mirrors adaptively bias other transistors to cover the lack of the CMFB circuit. To ensure stability, additional current sources are paralleled with the positive feedback structures. A high output voltage swing and a high DC gain are achieved by adding an adaptively biased common-source amplifier as the output stage leading to a class-AB operation. A large signal analysis, in weak inversion, is also done to mathematically describe both small- and large-signal characteristics. The proposed circuit was fabricated using TSMC$0.18 \mu \text{m}$CMOS technology occupying a silicon area of$113\,\,\mu \text{m}\,\,\times 70\,\,\mu \text{m}$. Experimental results at a supply voltage of 0.4 V show a gain bandwidth of 7 kHz, a DC gain of 60 dB, and a slew rate of 79 V/ms with just 24 nW power dissipation while driving a capacitive load of$2\times 15$pF.

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged with a conventional bulk-driven input differential pair using cross-coupled connections to significantly increase the transconductance. These circuitry ideas lead to an improvement in the amplifier's specifications, such as dc gain, slew rate (SR), and input noise without any degeneration in other parameters. Moreover, thanks to the use of the bulk terminals as the input nodes and also a simple common-source structure as the second stage, rail-to-rail input, and output swings are achieved, respectively. The proposed amplifier was fabricated in TSMC 0.18- μm CMOS technology. Under a supply voltage of 0.5 V, the measurement results show that the proposed amplifier achieves a dc gain of 78 dB, a gain bandwidth of 7.5 kHz, and an SR of 8.6 V/ms with just 91-nA current dissipation.