Resistive Random Access Memories (RRAMs) have been considered for implementing various emerging applications alongside storage. RRAMs offer the opportunity to address the Von Neumann bottleneck making the implementation of In-Memory Computing (IMC) possible. However, the exploration of RRAM potentials depends on being able to guarantee their reliability during lifetime. In this context, this paper investigates the impact of transistor aging on the behavior of 1T1R RRAM cells. A case study composed of an RRAM block, including peripherals, implemented using the 22 nm FDSOI GF technology is adopted. The obtained results indicate that the transistor aging, which was previously widely ignored, can lead to parametric degradation or even catastrophic faults. In addition, the obtained results show that the transistor type used for implementing the 1T1R RRAM cell, core or IO device, and operating temperature play important roles when analysing aging impact.

Abstract Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

Resistive Random Access Memories (RRAMs) are being commercialized with significant investment from several semiconductor companies. In order to provide efficient and high-quality test solutions to push high-volume production, a comprehensive understanding of manufacturing defects is significantly required. This paper identifies and characterizes the over-RESET phenomenon based on silicon measurements. In our case study, 30% cycles suffered from intermittent extremely high resistance state exceeding the high resistance state criteria. The paper shows the limitations of conventional defect modeling based on linear resistors. To address this challenge, the Device-Aware (DA) defect modeling method is applied; a model of the defective RRAM device is developed and calibrated using measurements to accurately describe the impact of the defect on the electrical behavior of the memory device. Afterward, fault analysis is performed based on the DA defect model, and appropriate fault models are introduced; they show that the DA defect model will sensitize deep (extremely high resistance) state faults. Finally, dedicated test solutions for over-RESET devices are proposed.

Over the last fifty years, Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down according to the predictions made by Gordon Moore in the 1960s, hence making the design of high-performance applications possible. However, there is a growing concern that device scaling will become infeasible below a certain feature size. In parallel, emerging applications present high demands regarding storage and computing capability, combined with challenging constraints in terms of size, power consumption, and response latency. Thus, memristive devices have become promising candidates to complement or replace the CMOS technology due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability and density, as well as their capability to implement high-density memories as well as new computing paradigms. Despite these advantages, memristive devices are also suscreptible to manufacturing defects that may cause faulty behaviors not observed in CMOS, significantly increasing the test complexity. This paper presents the validation of a Design-for-Testability (DFT) strategy for Resistive Random Access Memories (RRAMs). The proposed strategy, able to detect traditional and unique faults in RRAM cells, has been implemented using an X-Fab technology library and validated based on a simplified case study. The obtained results show that the idea of applying a predefined operating sequence in combination with electrical measurements can guarantee the detection of unique faults in RRAM cells.

Abstract Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

Abstract Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. Despite demonstrating improvements on short channel effect and overcoming the growing leakage problem of planar CMOS technology, the continuity of feature size miniaturization tends to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs). Variation during the manufacturing process has introduced different types of defects that directly affect the SRAM's reliability, such as weak resistive defects. As some of these defects may cause dynamic faults, which require more than one consecutive operation to sensitize the fault at the logic level, traditional test approaches may fail to detect them, and test escapes may occur. These undetected faults, associated with weak resistive defects, may affect the FinFET-based SRAM reliability during its lifetime. In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects. Firstly, a TCAD model of a FinFET-based SRAM cell is proposed allowing the evaluation of the ionizing particle’s impact. Then, SPICE simulations are performed considering the current pulse parameters obtained with TCAD. In this step, weak resistive defects are injected into the FinFET-based SRAM cell. Results show that weak defects can positively or negatively influence the cell reliability against SEUs caused by ionizing particles.

The miniaturization of CMOS technology is likely to reach its limit due to short-channel effects. New transistor technologies, including FinFET technology, were developed to deal with this effect and enable the continuous scaling-down of technological nodes. Alongside the constant scale-down of integrated circuits technology, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). The manufacturing process variation has introduced different types of defects that directly affect the SRAM's reliability. Thus, it remains unknown if fault models used to characterize faults in CMOS memory circuits are sufficiently accurate to represent the behavior of FinFET-based memories. In this context, a study of functional implications of manufacturing resistive defects in FinFET-based SRAMs is presented. In more detail, a fault model for FinFET-based SRAMs as well as a complete analysis of the static and dynamic fault behavior are presented. The proposed analysis has been performed by means of SPICE simulations, adopting a 20nm technology library. The faults were categorized in single and coupling, static and dynamic faults.

Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced VTHp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.

Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which accelerates memory cells aging. This paper proposes a new approach to detect SRAM aging during system lifetime based on an On-Chip Aging Sensor (OCAS). The OCAS is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS every SRAM column, each periodically performing off-line tests by monitoring the write operations on the SRAM cells in order to detect aging. To prevent the OCAS from aging and from dissipating leakage power, the OCAS circuitry is powered-off during its idle periods. Experimental results demonstrate the sensor's high sensitivity to detect early aging states and therefore, guaranteeing high memory reliability. Finally, the area overhead related to the sensors' insertion is almost negligible.