A subband decomposition using wavelet filters has become an effective basis for image compression. The use of a ladder structure for the subband filtering provides a fast implementation and allows the system to be useful at video rates. A system is proposed that provides good quality video for moderate motion, roughly common intermediate format-f 0-t (CIF-) sized images at bit rates under 500 kb/s, and for teleconferencing scenes at bit rates from 180 kb/s to below 128 kb/s (basic rate ISDN). The system uses subband coding, a modified version of H.261, and entropy-constrained quantization to achieve the desired bit rate and image quality.

The design of image prefilters for error control is considered and seen to be dual to the well-known problem of designing anti-aliasing filters for signal decimation. Filters formed from unitary transforms are seen to yield computationally efficient two-step implementations obtained by orthogonal decomposition. Filters which perform optimally in the presence of background noise are introduced and seen to require only P multiplications for each column of N pixels, where P=2 and N=240 for TV signals in NTSC format. The amount of signal distortion due to this prefiltering is small and often imperceptible.>

The design of image prefilters for error control is considered and seen to be closely related to the problem of designing antialiasing filters to precede signal decimation. Intrafield codes are introduced, some of which can be implemented with fewer than 1 multiplier per 100 pixels. These codes have a great advantage in a bandlimited TV environment over alternative error-control methods requiring no redundancy, since they depend on prefiltering of the image. The primary implementation cost is, therefore, that of intrafield processors at the source and receiver. These processors consist primarily of a field store and of simple arithmetic units implementing vertical line (comb). filtering. In the optimal filters discussed, most coefficients are +or-1's. An application to compatible coding of TV signals for control of impulse errors in NTSC signals is presented. The emphasis is on encoding by vertical filtering and burst error estimation.>

An approach to the simulation of distributed signal processing systems using a standard, general-purpose programming language is described. The models for both the simulator and the hardware system to be simulated are discussed. It was seen that the use of a language which supports processes in conjunction with the use of the process interaction simulation model contributes to convenient and accurate simulations.

Error-correcting codes defined over the real-number and complex-number fields are introduced. The possibility of utilizing realnumber arithmetic permits the codes to be implemented with operations normally available in standard programmable digital signal processors by methods which are discussed. Hadamard and discrete Fourier transform codes are presented for block coding, and the latter are seen to be cyclic and to include the class of BCH codes. It is shown that maximum distance separable real-number BCH (N, K) codes exist for all nontrivial values ofNandK. A large class of block and convolutional real-number single-error-correcting codes, derived from similar codes overGF(p), are presented. Both block and convolutional codes are seen to be describable by thez-transform in a manner which emphasizes their similarities to conventional digital signal processing structures such as digital filters and digital filter banks. Methods for correcting weighttandt + 1errors in aterror-correcting code are demonstrated and interpreted; in particular, the use of a VLSI digital signal processor for implementation of an algorithm for correcting almost all double adjacent error patterns in a single-error-correcting convolutional code is discussed.

Signal processing structures, incorporating one and two digital filter banks (DFB's), are examined with the aid of a polyphase transform that is defined. Convenient matrix descriptions for DFB structures and the short-time Fourier transform are obtained. A condition for decimation in DFB's without aliasing is obtained and shown to be equivalent to shift invariance. Certain commonly employed filter banks with real and complex structures age seen to admit realization with the low noise, memory efficient SIDO filter structure.

A 12-channel TDM/FDM translator consisting of six VLSI digital signal processors is described. A filter bank which consists of a discrete cosine transform and a polyphase network of 14 filters is realized by three processors and effects the translation each way. One processor provides synchronization between the 96 kHz TDM and 112 kHz FDM signals and performs the cosine transform, and the remaining two do the filtering. The polyphase procedure is reviewed, a simplified development of the fast discrete cosine transformation is presented, and a new structure for the filters is introduced. The main opportunities for computational reduction are seen to be in the filtering. An algorithm for the filters is presented which is optimal with respect to efficiency and roundoff noise for a processor with a single multiplier accumulator. The VLSI processors discussed are seen to be very effective in this realization because of their efficiency in this type of filtering and because of their intercommunication and synchronization capabilities.