The increasing susceptibility of aerospace integrated circuits (ICs) to single-event effects (SEEs) demands advanced radiation-hardening-by-design (RHBD) methodologies, especially for analog/mixed-signal circuits operating in extreme environments. While digital circuit hardening has seen extensive advancements, circuit-level radiation hardening techniques specifically targeting analog building blocks—such as high-speed current-mode logic (CML) latches used in frequency dividers—have received relatively less attention, largely due to the inherent trade-offs between radiation tolerance and high-speed performance. This work proposes a low-overhead RHBD strategy for CML latches in high-speed dividers, addressing single-event upsets (SEUs) through the integration of pMOS transistors at storage nodes to counteract charge collection induced by SEEs. The methodology is rigorously validated using calibrated double-exponential current source simulations, emulating SEEs. The hardened design demonstrates robust radiation tolerance across varied pMOS control signals and sizing parameters, with minimal sensitivity introduced at additional nodes. Postlayout simulations in sub-20 nm FinFET technology reveal a maximum operating frequency of 46 GHz, accompanied by ultralow implementation overheads: a 2% area penalty and 22% power increase. The strategy resolves critical trade-offs between radiation resilience and high-speed performance, offering a scalable solution for aerospace-grade circuits in radiation-intensive environments. This advancement underscores the viability of tailored RHBD approaches for analog/mixed-signal systems, enabling next-generation space electronics that harmonize reliability with cutting-edge functionality.

The conventional D-type flip-flop (DFF) is sensitive to the particle induced Single Event Upsets (SEUs). Thus, the radiation tolerance improvements for flip-flops by using novel layouts have attracted considerable interests in space application. In this paper, the SEU hardened fishbone layouts are proposed and employed to the delay module and slave latch cells in our test chip, and the width of radiation induced transient pulses is analyzed by our detailed characterizations. The actual radiation sensitivities of the new layouts are also evaluated by our systematic heavy ion experiments. Without additional consumption of transistors for the basic Double Interlocked Storage Cell (DICE), the obvious enhancements of SEU tolerance for the fishbone layouts are verified under static tests, though the initial clock signal has significant influence on SEU cross sections. The consistent SEU mitigation results of the employed fishbone layout for both the delay module and flip-flop cell indicate that the novel structure may be suitable for harsh radiation environment.