In this work, a novel signal processing approach for the efficient computation of the cross-correlation operator on low-complexity FPGAs is presented. Sets-Of-Real-Numbers (SORNs) arithmetic is exploited to build resource-efficient multipliers that are carefully injected into the hardware architecture. By this measure, a significant decrease of arithmetic hardware requirements is achieved. Especially, in the scope of low-complexity FPGAs, this depicts an enormous advantage, as these devices usually only have a few or even no specific arithmetic hardware accelerators, such as DSP blocks, at all. In order to smoothly integrate these special multipliers, additional conversion functions are needed to handle the number format transformation between SORNs and the fixed-point (FxD) data representation. For the evaluation, several cross-correlation-related hardware architectures with different number formats, data types, and multipliers are taken into account. Out of this, the proposed SORN-based implementation turns out to achieve extremely high performance regarding the resulting signal quality. In terms of the resource utilization, it clearly outperforms the traditional FxD-based architectures. Hence, SORN-based multipliers identify as a powerful extension for calculating the cross-correlation on low-complexity FPGAs.

We propose a comprehensive health monitoring of astronauts which is based on Ballistocardiography (BCG). BCG uses high-precision accelerometers to measure the motion of the heart at the body surface. In contrast to conventional methods (e.g. Electrocardiography (ECG)), BCG enables the derivation of heart-related parameters that can otherwise only be recorded by imaging methods such as echocardiography. A huge issue is the signal quality of the acceleration measurement, however, by means of differential arrangement of digital acceleration sensors, the signal quality and also the susceptibility to interference can be reduced when measuring the smallest accelerations. In preparation for a BCG experiment on the International Space Station (ISS), a pre-flight measurement system was developed whose architectural design is similar to the flight hardware, but extended by a reference ECG. To simplify measurement campaigns, the simultaneously recorded BCG and ECG data can be visualized in real time, which will be shown in this demo.

Comprehensive health monitoring is highly relevant for the safety of manned spaced missions. Ballistocardiography (BCG) is a method for providing information of the heart physiology by measuring accelerations on the body surface that are caused by forwarded heart and blood movements in the vascular system. In order to provide a sensor system with a high signal quality, this paper presents differential BCG sensing at the system level for digital accelerometers and its integration into a sensing system. The system is part of a running experiment of the Cosmic Kiss mission on the International Space Station (ISS). Compared to single sensor solutions, the noise power scales down to about 50%, the Signal to Noise Ratio (SNR) is increased by a factor of 1.87 and the BCG signal variability especially improves for diastole area. Furthermore, by exploiting differential sensing techniques, both high reliability is achieved and common mode interference is mitigated, which is of high importance within the scope of space applications. Beside the presentation of the entire wireless sensor system including differential sensing approach, pre-processing unit and Ultra Wideband (UWB) communication module, results of the pre-flight tests show the performance of the system as well as the suitability for targeted mission.

SORN Arithmetic is a low-complexity and low-precision digital number format based on intervals that can be useful for preprocessing large datasets. Since the interval width of a SORN result is likely to grow with the number of operations, the concept of fused SORN operations is proposed. Functions with more than one operation are evaluated without intermediate quantization, reducing spurious interval growth (the “dependency problem”) and increasing the resulting precision. The presented evaluations for basic and complex fused functions show a reduction of the output interval widths of up to 53%. In addition, introducing fused SORN operations also leads to significant hardware reductions in area, power consumption and path delay. Compared to the non-fused designs, reductions of the Area-Power-Timing-product of up to 88% can be achieved.

Sets-Of-Real-Numbers (SORN) Arithmetic derives from the Unum type-II number format and provides high throughput and low complexity computations at the cost of a very rough resolution. This work presents a symbol detection unit for MIMO transmission with a BPSK modulation which consists of a SORN preprocessor applying an exhaustive search method and a fixed-point module processing the results from the SORN unit. Different SORN datatypes and hardware configurations are considered and evaluated throughout BER simulations and postsynthesis analyses.

In this paper different SORN (Sets Of Real Numbers) datatype configurations are analyzed for unum type-2-based arithmetic applied to symbol detection in a wireless MIMO communication system. Different SORN interval properties and MIMO-specific performance measures as well as the corresponding hardware architectures are evaluated in order to rate the suitability of the different configurations for the target application. The evaluation of the proposed datatypes indicates an improvement in the solution set reduction of up to 95.4 % and a hardware complexity reduction of 30.3 % comparing the proposed 17 bit configuration to the original unum type-2-based 16 bit SORNs.

This article provides an efficient hardware generator for high-performance sets-of-real-numbers (SORNs) arithmetic. Complex datapaths are automatically built in VHDL, comprising the generation of arithmetic operations and functions as well as all necessary interconnects. Various SORN datatypes can be easily set up enabling high adaptivity to different applications. For further performance improvements additional optimization and implementation techniques are considered as well. For evaluation, a SORN-based symbol detector for a multiantenna wireless communication scenario is generated that solves a system of linear equations. As SORN-based signal processing allows a quick but rough calculation of the system equations outcome, it can be exploited to reject possible input vectors that do not satisfy the general constraints of the signal detection task. Hence, this generally leads to a heavily reduced set of remaining solutions. Multiple hardware architectures with different SORN datatypes are generated and compared. Further, an analysis is performed considering the signal-to-noise ratio (SNR). Finally, logic synthesis is applied to selected designs and compared to references from the literature highlighting this article to be highly hardware-efficient and suitable for application-specific signal processing.

The Blockchain technology has become one of the most groundbreaking discoveries of the last decade, encompassing a secure and distributed exchange of digital resources. By now, a large variety of applications and topics have been identified which have proven its feasibility. In this paper we discuss the deployment of Blockchains to manage concurrent industrial wireless premises networks. We propose a simple example of a Smart Contract protocol for distributed resource allocation, forcing the participants to reach an agreement on the wireless channel usage. A simple simulation model is set up highlighting Blockchain-based consensus findings as a promising approach for autonomous resource allocation within this application.

Massive MIMO systems have become more popular in wireless communications due to their improved spectral efficiency compared to existing small-scale MIMO systems. However, current estimation methodes take too long for larger numbers of antennas. In this paper, a near-optimal iterative linear signal detection for massive MIMO is introduced exploiting the random projection method to approximate the channel matrix in a significantly lower dimensional space. This is then used as a preconditioner in the conjugate gradient least squares algorithm to enhance the convergence rate. For evaluation, different scenarios of spatial correlation in a massive MIMO system are considered. In contrast to other low-complexity signal detectors, our approach achieves excellent results in terms of robustness and determined latency.

Efficient signal processing takes a key role in application-specific circuit design. For instance, future mobile communication standards, e.g., high-performance industrial mobile communication, require high data rates, low latency and/or high energy-efficiency. Hence, sophisticated algorithms and computing schemes must be explored to satisfy these challenging constraints. In this paper we leverage the paradigm of approximate computing to enable hardware-efficient QR-decomposition for channel pre-coding. For an efficient computation of the Givens-Rotation, bivariate, non-linear numeric functions are taken into account. An effective design method is introduced leading to highly adapted (special-purpose) functions. For evaluation, our work is tested with different configurations in a Tomlinson-Harashima pre-coding downlink environment. In addition, a corresponding HDL implementation is set up and logic and physical CMOS synthesis is performed. The comparison to actual references prove our work to be a powerful approach for future mobile communication systems.

In this paper we propose a QR-decomposition hardware implementation that processes complex calculations in the logarithmic number system. Thus, low complexity numeric format converters are installed, using nonuniform piecewise and multiplier-less function approximation. The proposed algorithm is simulated with several different configurations in a downlink precoding environment for 4×4 and 8×8 multi-antenna wireless communication systems. In addition, the results are compared to default CORDIC-based architectures. In a second step, HDL implementation as well as logical and physical CMOS synthesis are performed. The comparison to actual references highlight our approach as highly efficient in terms of hardware complexity and accuracy.

Time and frequency synchronisation are significant parts of the cell-search procedure and one of the first processing blocks within a mobile communication system. Particularly for an OFDM transmission within an initial synchronisation process, the algorithm has to deal with carrier frequency offsets up to several subcarrier spacings. To be able to still operate under those conditions, the cell-search procedure consists of different processing steps, combined in a hybrid algorithm. Beside good performance properties, hybrid algorithms lead to a high computational demand and implementation effort. To overcome these challenges, flexible architectures, which are able to select the most suitable algorithm during runtime, are the base for an efficient hardware realization. In this paper, as an example, we are introducing an hybrid initial synchronisation algorithm for an LTE-system, which still operates under the effect of a carrier frequency offset greater than the subcarrier spacing. Consecutively, we are showing a reconfigurable architecture as well as the results of an FPGA implementation of the time synchronisation part of that algorithm. The architecture is able to switch between different correlators, namely a reverse-auto, a cross- and a CP-based auto-correlation during runtime, which enables a flexible and low complexity realization of the computational complex synchronisation process.