Bérenger Bramas

dblp:116/2998 · DBLP profile ↗
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9ranked-venue papers
2as first author
5since 2021 · last 2025
0000-0003-0281-9709ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 8 · 2 first-author · 4 since 2021Software engineering, systems software and programming languages · 2 · 2 since 2021
YearPublicationVenuePosition
2025 InteropUnityCUDA: A Tool for Interoperability Between Unity and CUDA
abstract
ABSTRACT Introduction Unity is a powerful and versatile tool for creating real‐time experiments. It includes a built‐in compute shader language, a C‐like programming language designed for massively parallel General‐Purpose GPU (GPGPU) computing. However, as Unity is primarily developed for multi‐platform game creation, its compute shader language has several limitations, including the lack of multi‐GPU computation support and incomplete mathematical libraries. Contribution To address these limitations, GPU manufacturers have developed specialized programming models, such as CUDA and HIP, which enable developers to leverage the full computational power of modern GPUs. This article introduces an open‐source tool designed to bridge the gap between Unity and CUDA, allowing developers to integrate CUDA's capabilities within Unity‐based projects. Methods The proposed solution establishes an interoperability framework that facilitates communication between Unity and CUDA. The tool is designed to efficiently transfer data, execute CUDA kernels, and retrieve results, ensuring seamless integration into Unity's rendering and computation pipeline. Results Our tool extends Unity's capabilities by enabling CUDA‐based computations, overcoming the inherent limitations of Unity's compute shader language. This integration allows developers to exploit multi‐GPU architectures, leverage advanced mathematical functions, and enhance computational performance for real‐time applications.
David Algis, Bérenger Bramas, Emmanuelle Darles, Lilian Aveneau
Softw. Pract. Exp.2
2024 Autovesk: Automatic Vectorized Code Generation from Unstructured Static Kernels Using Graph Transformations
abstract
Leveraging the SIMD capability of modern CPU architectures is mandatory to take full advantage of their increased performance. To exploit this capability, binary executables must be vectorized, either manually by developers or automatically by a tool. For this reason, the compilation research community has developed several strategies for transforming scalar code into a vectorized implementation. However, most existing automatic vectorization techniques in modern compilers are designed for regular codes, leaving irregular applications with non-contiguous data access patterns at a disadvantage. In this article, we present a new tool, Autovesk, that automatically generates vectorized code from scalar code, specifically targeting irregular data access patterns. We describe how our method transforms a graph of scalar instructions into a vectorized one, using different heuristics to reduce the number or cost of instructions. Finally, we demonstrate the effectiveness of our approach on various computational kernels using Intel AVX-512 and ARM SVE. We compare the speedups of Autovesk vectorized code over GCC, Clang LLVM, and Intel automatic vectorization optimizations. We achieve competitive results on linear kernels and up to 11× speedups on irregular kernels.
Hayfa Tayeb, Ludovic Paillat, Bérenger Bramas
ACM Trans. Archit. Code Optim.3
2023 Lifting Code Generation of Cardiac Physiology Simulation to Novel Compiler Technology
abstract
The study of numerical models for the human body has become a major focus of the research community in biology and medicine. For instance, numerical ionic models of a complex organ, such as the heart, must be able to represent individual cells and their interconnections through ionic channels, forming a system with billions of cells, and requiring efficient code to handle such a large system. The modeling of the electrical system of the heart combines a compute-intensive kernel that calculates the intensity of current flowing through cell membranes, and feeds a linear solver for computing the electrical potential of each cell.
Arun Thangamani, Tiago T. Jost, Vincent Loechner, Stéphane Genaud, Bérenger Bramas
CGO5
2023 GPU Code Generation of Cardiac Electrophysiology Simulation with MLIR
Tiago T. Jost, Arun Thangamani, Raphaël Colin, Vincent Loechner, Stéphane Genaud, Bérenger Bramas
Euro-Par6
2021 TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale
abstract
To achieve high performance and high energy efficiency on near-future exascale computing systems, three key technology gaps needs to be bridged. These gaps include: energy efficiency and thermal control; extreme computation efficiency via HW acceleration and new arithmetics; methods and tools for seamless integration of reconfigurable accelerators in heterogeneous HPC multi-node platforms. TEXTAROSSA aims at tackling this gap through a co-design approach to heterogeneous HPC solutions, supported by the integration and extension of HW and SW IPs, programming models and tools derived from European research.
Giovanni Agosta, Daniele Cattaneo 0002, William Fornaciari, Andrea Galimberti, Giuseppe Massari, Federico Reghenzani, Federico Terraneo, Davide Zoni, Carlo Brandolese, Massimo Celino, Francesco Iannone, Paolo Palazzari, Giuseppe Zummo, Massimo Bernaschi, Pasqua D'Ambra, Sergio Saponara, Marco Danelutto, Massimo Torquati, Marco Aldinucci, Yasir Arfat, Barbara Cantalupo, Iacopo Colonnelli, Roberto Esposito, Alberto Riccardo Martinelli, Gianluca Mittone, Olivier Beaumont, Bérenger Bramas, Lionel Eyraud-Dubois, Brice Goglin, Abdou Guermouche, Raymond Namyst, Samuel Thibault, Antonio Filgueras, Miquel Vidal, Carlos Álvarez 0001, Xavier Martorell, Ariel Oleksiak, Michal Kulczewski, Alessandro Lonardo, Piero Vicini, Francesca Lo Cicero, Francesco Simula, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Pier Stanislao Paolucci, Matteo Turisini, Francesco Giacomini, Tommaso Boccali, Simone Montangero, Roberto Ammendola
DSD27
2017 Bridging the Gap Between OpenMP and Task-Based Runtime Systems for the Fast Multipole Method
abstract
With the advent of complex modern architectures, the low-level paradigms long considered sufficient to build High Performance Computing (HPC) numerical codes have met their limits. Achieving efficiency, ensuring portability, while preserving programming tractability on such hardware prompted the HPC community to design new, higher level paradigms while relying on runtime systems to maintain performance. However, the common weakness of these projects is to deeply tie applications to specific expert-only runtime system APIs. The OpenMP specification, which aims at providing common parallel programming means for shared-memory platforms, appears as a good candidate to address this issue thanks to the latest task-based constructs introduced in its revision 4.0. The goal of this paper is to assess the effectiveness and limits of this support for designing a high-performance numerical library, ScalFMM, implementing the fast multipole method (FMM) that we have deeply re-designed with respect to the most advanced features provided by OpenMP 4. We show that OpenMP 4 allows for significant performance improvements over previous OpenMP revisions on recent multicore processors and that extensions to the 4.0 standard allow for strongly improving the performance, bridging the gap with the very high performance that was so far reserved to expert-only runtime system APIs.
Emmanuel Agullo, Olivier Aumage, Bérenger Bramas, Olivier Coulaud, Samuel Pitoiset
IEEE Trans. Parallel Distributed Syst.3
2016 Task-based FMM for heterogeneous architectures
abstract
Summary High performance fast multipole method is crucial for the numerical simulation of many physical problems. In a previous study, we have shown that task‐based fast multipole method provides the flexibility required to process a wide spectrum of particle distributions efficiently on multicore architectures. In this paper, we now show how such an approach can be extended to fully exploit heterogeneous platforms. For that, we design highly tuned graphics processing unit (GPU) versions of the two dominant operators P2P and M2L) as well as a scheduling strategy that dynamically decides which proportion of subsequent tasks is processed on regular CPU cores and on GPU accelerators. We assess our method with the StarPU runtime system for executing the resulting task flow on an Intel X5650 Nehalem multicore processor possibly enhanced with one, two, or three Nvidia Fermi M2070 or M2090 GPUs (Santa Clara, CA, USA). A detailed experimental study on two 30 million particle distributions (a cube and an ellipsoid) shows that the resulting software consistently achieves high performance across architectures. Copyright © 2015 John Wiley & Sons, Ltd.
Emmanuel Agullo, Bérenger Bramas, Olivier Coulaud, Eric Darve, Matthias Messner, Toru Takahashi 0002
Concurr. Comput. Pract. Exp.2
2015 Time-domain BEM for the wave equation on distributed-heterogeneous architectures: A blocking approach
Bérenger Bramas, Olivier Coulaud, Guillaume Sylvand
Parallel Comput.1
2014 Time-Domain BEM for the Wave Equation: Optimization and Hybrid Parallelization
Bérenger Bramas, Olivier Coulaud, Guillaume Sylvand
Euro-Par1