In this paper, we propose a software based technique to reveal the DRAM geometry information which is essential in studying various memory based attacks mounted on embedded devices such as Row Hammer. We apply a reverse-engineering approach for retrieving row, column, bank bits of DRAM which may significantly increase the number of bit flips in a Row Hammer test. To the best of our knowledge, the proposed technique is the first work to disclose the entire information about the DRAM chips of any embedded architecture.

Abstract Class diagrams, being more illustrative, provide an easier way of understanding software requirements compared to use case descriptions. Both manual and automated methods are used for the extraction of class diagrams from requirements. The automated techniques employ certain extraction rules and natural language processing methods. Each use case description template introduces a small set of extraction rules. However, when all types of templates are considered, the number of rules becomes large and the procedure becomes tedious. Thus, researchers restricted the class diagram extraction procedure to some specific use case description templates. However, such a restriction negatively affects the software developers as they get restricted to working with only limited templates. The proposed work in this paper strives to remove this restriction on developers by introducing an intermediate template. The traditional use case description templates get transformed into the intermediate template and the rule extraction procedure is then applied to this intermediate template. This reduces the total number of extraction rules and hence, brings down the extraction complexity. The class diagrams extracted from use case description templates of different domains using proposed technique show more accuracy in terms of completeness and correctness when compared with the state of the art approaches.

The software requirement specifications are usually documented either in unstructured, semi structured or structured format. The requirements specified in unstructured format are written in simple continuous paragraph and the structured format specifies requirements by means of diagrams. The semi-structured format represents requirements with the help of some keywords. Literature suggests that the rule based work has been the common choice for unstructured format of documenting. However, these rule based works do not yield satisfactory results for semi-structured format. Consequently, these rules need to re-framed in order to apply them for the semi-structured formatted documents. In this paper, we present an improvement on the existing rules considering the keywords present in the text. The technique involves automatic extraction of the class diagrams using NLP tools and techniques. Along with existing rules, the newly formulated rules have been tested for different case studies and suitable metrics have been devised to evaluate the obtained results. Results show that the automatically generated class diagram have 82% average precision value and 94% average recall value when compared to the class diagrams generated by the human experts.

This brief proposes an on-line transparent test technique for detection of latent hard faults which develop in first-input first-output buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test algorithm has been integrated into the router-channel interface and on-line test has been performed with synthetic self-similar data traffic. The performance of the NoC after addition of the test circuit has been investigated in terms of throughput while the area overhead has been studied by synthesizing the test hardware. In addition, an on-line test technique for the routing logic has been proposed which considers utilizing the header flits of the data traffic movement in transporting the test patterns.

This paper proposes a distributed Memory Built- In-Self Test (MBIST) architecture employing a hybrid technique for testing heterogeneous memory cores interconnected using NoC. In the proposed architecture, the memory cores are placed in different groups based on distance and timing constraints. Each group has a dedicated BIST controller which performs parallel March test on all the cores in a group while the groups are tested in a pipeline. The paper also proposes a test schedule for the proposed architecture to keep the test power within the power budget. Experiments performed on ITC'02 benchmark circuit confirms that our proposed test schedule performs a more power constrained test as compared to dedicated BIST technique. Moreover, experimental results indicate real estate benefits for the proposed distributed BIST architecture in comparison to other reported techniques.