Cellular Automata (CA) is attractive for high-speed VLSI implementation due to modularity, cascadability, and locality of interconnections confined to neighboring logic cells. However, this outcome is not easily transferable to tree-structured CA, since the neighbors having half and double the index value of the current CA cell under question can be sufficiently distanced apart on the FPGA floor. Challenges to meet throughput requirements, seamlessly translate algorithmic modifications for changing application specifications to gate level architectures and to address reliability challenges of semiconductor chips are ever increasing. Thus, a proper design framework assisting automation of synthesizable, delay-optimized VLSI architecture descriptions facilitating testability is desirable. In this article, we have automated the generation of hardware description of tree-structured CA that includes a built-in scan path realized with zero area and delay overhead. The scan path facilitates seeding the CA, state modification, and fault localization on the FPGA fabric. Three placement algorithms were proposed to ensure maximum physical adjacency amongst neighboring CA cells, arranged in a multi-columnar fashion on the FPGA grid. Our proposed architectures outperform implementations arising out of standard placers and behavioral designs, existing tree mapping strategies, and state-of-the-art FPGA centric error detection architectures in area and speed.

Random number generation is integral to information security in IoT based cyber-physical systems. One such recent scheme of random number generation was proposed in [1] called Mageto, which is based on the design principles of cellular automata (CA). CA are characterized as finite state machines (FSMs) which evolve in discrete time steps. In hardware, their architecture remains modular and cascadable, which is ideal for amicable mapping onto FPGA primitives, leading to a speed-area efficient realization [2], [3]. Fault localization and in-system testing of FPGAs are now assuming substantial importance [4]. Exploring the utilization ratio of the configured primitives is often essential for supplementing an original FPGA implementation with testable logic without appreciable hardware overhead and critical path delay, by adopting careful optimization practices. Primitive instantiation is one such technique to directly instantiate an FPGA primitive into a design through appropriate logic configuration. We believe that VLSI implementation of Mageto has never been discussed before, which we choose to address in this paper. Our proposed primitive instantiation based architectures for Mageto, whose design description generation has been automated, outperform the relatively high level behavioral implementations with respect to area (logic slices) and speed.

VLSI implementation of Cellular Automata (CAs) has gained importance owing to its features which guarantee parallelism, locality and structural regularity. In this work, we have addressed the design challenges pertaining to an implementation optimized for speed, of tree-structured linear CA architectures on Field Programmable Gate Array (FPGA) with built-in scan paths. Scan based design facilitates state initialization, helps to escape from any graveyard state, or figure out faulty locations (if any) on which the circuit is mapped. Our design automation platform generates synthesizable circuit descriptions of tree-structured CA on FPGA, and appends scan functionality without additional logic or speed overhead. Placement algorithms governing the map of CA cell nodes on the FPGA slices have been proposed to ensure maximum physical proximity among CA cells sharing neighborhood dependencies. This is done to exploit the VLSI amenable features such as physical adjacency of the neighboring nodes participating in the next state (NS) computation of each other. The ultimate implementation leads to minimum spacing of linear order between CA neighbours. The NS logic of each CA cell inclusive of scan multiplexing, owing to restricted neighborhood size, is realized using a single Look-Up Table. Our architectures outperform behavioral implementations realized with higher levels of design style abstraction.

Scan based error detection architectures for hybrid, carry-free radix-2 and radix-4 addition operations using redundant arithmetic are presented in this paper. Such addition operations have been chosen as representative examples as they are free from carry propagation delay and are ideal from the viewpoint of technology mapping of the logic elements onto the FPGA slices. The architectures have been conceived following the design paradigm of target FPGA specific primitive instantiation coupled with location constraints, without any degradation in the speed of circuit operation as compared to the original circuit implementation without the scan operation. Our architectures also comfortably outperform the existing state-of-the-art error detection architectures in terms of speed and consumes less area.

We present the principles of operation and functioning of a CAD software tool for the automated realization of high performance integer arithmetic circuits targeting Xilinx Field Programmable Gate Arrays (FPGAs). The key ideas behind the improvement of circuit performance are optimal usage of the hardware primitives available on the Xilinx FPGA platform, as well as regular, careful and constrained placement of the circuit building blocks on the FPGA fabric. The bit - sliced architectures of our proposed designs allow us to automatically generate synthesizable, platform - specific structural Hardware Description Language (HDL) code for the proposed circuits, as well as the placement constraint files needed to control the placement of the design on the given FPGA fabric. Compared against circuits implemented using existing approaches and those automatically generated using existing CAD tools, our automatically generated implementations demonstrate significant speed improvement.