This paper presents novel hardware architectures for Midori, a lightweight symmetric block cipher optimized for low-energy edge computing applications. To enhance the efficiency of the Midori-64 variant, the architecture has been redesigned with a 16-bit datapath. The proposed design adopts a hybrid approach, combining parallel and serial data processing to meet the demands of encryption. Specialized selector units are integrated into the architecture to streamline this process, resulting in improved performance while maintaining a compact footprint. In addition to architectural enhancements, a masking countermeasure has been incorporated into the S-boxes of Midori to strengthen resistance against side-channel power analysis attacks. The masked S-boxes were initially integrated into the cipher’s substitution-permutation network (SPN), forming a secure variant of the core transformation layer. This modified SPN was subsequently embedded into the proposed Midori-64 architecture, and the associated performance and area overheads were systematically evaluated. The proposed masked S-boxes have an area reduction of 55.7%, power reduction of 62.38% and energy reduction of 78.2% compared to other masked designs. These significant improvements come with a 50% reduction in area overheads and a 7% reduction in delay overheads when compared to the current state-of-the-art masked designs with respect to the unmasked designs. We also evaluated the modified, overall masked and unmasked encryption architecture for Midori-64 on Nexys4 DDR FPGA and for standard cell libraries. Our findings indicate that the proposed masked designs offer improved performance with significantly reduced overheads compared to their unmasked counterparts. The FPGA-based implementations have proven to be better for the low area and high throughput requirements for a constrained device in IoT applications. Moreover, the resiliency of the proposed masked S-boxes to the differential power analysis attack has been explored and demonstrated in detail in this paper.

Air pollution monitoring systems are essential for evaluating rural and industrial environmental quality for safeguarding public health. This study presents a comprehensive IoT-based framework that uses low-cost sensors and machine learning algorithms for real-time monitoring of various pollutants, including LPG, methane, CO, alcohol, PM2.5, PM10, temperature, and humidity. The system gathers sensor data from a gateway node, which is then processed using Support Vector Machines (SVM) and Random Forest Regression (RFR) models to predict pollutant concentrations. Our approach features innovative methodologies for data validation, anomaly detection, and predictive modeling, employing Root Mean Squared Error (RMSE) as the performance metric. The model achieved a remarkably low RMSE value of 0.022, significantly improving the accuracy and reliability of air quality assessments. Experimental results highlight the system's capability to capture complex environmental patterns and predict pollutant levels with high precision. This research intends air pollution monitoring from cost-effective Internet of Things (IoT) solutions and machine learning techniques. Additionally, the user interface is designed for mobile applications, offering real-time data access, alerts, and notifications, thereby enabling personalized environmental health management and targeted pollution control strategies in industrial areas.

Street lighting is one of the prominent applications that demand a massive amount of power and substantially contributes to the energy budget of a country. Light Emitting Diode (LED) and the advancement of Internet of Things (IoT) have significantly improved conventional street light technology. Nevertheless, the rapid growth of IoT devices has presented a formidable challenge in powering the vast array of IoT devices. In this manuscript, a sustainable, battery-free, low-power street light management system has been proposed which is powered from hybrid solar and solar thermal energy harvesting scheme integrated with an efficient power management unit. As a specific case study, the prototype has been implemented with an existing LED street light in India. The characteristics and performance of the prototype have been evaluated to ensure its seamless operation under real-world scenarios. The average power consumption of the system is measured as 2.088 mW when operating in real-time with 50% duty cycle, exhibiting high Quality of Service (QoS). It features long-range communication up to 761 m through implementing LoRaWAN technology. Dimension of the prototype has been restricted to 10.5 cm x 6.5 cm x 2.3 cm to make it suitable for retrofitting with existing LED based street lights

Electrocardiogram (ECG) signals are vital features to identify a healthy body; diagnosing cardiovascular diseases (CVDs) automatically using computer-aided tools has caught a significant attention in the current medical scenario. In recent times with the rapid growth of smart health-care system, IoT enabled edge devices make it possible for early diagnosis of diseases with resource constraint devices. PYNQ- a Python productivity on Xilinx platform, based hybrid CNN architecture has been proposed in this work for classifying arrhythmia in reference to AAMI (Association for the Advancement of Medical Instrumentation) EC57 standard. A comparative investigation is conducted on volume of trainable parameters of the architecture, and accuracy of ECG classification. A customized FPGA IP for the proposed hybrid 1-D CNN architecture has been generated using Vitis High Level Synthesis (HLS) tool that would be implemented on PYNQ-Z2 board. A lightweight cryptographic algorithm ASCON has been used in the proposed framework, wherein an authentication-based scheme for verifying an individual, via corresponding ECG signals is used, prior to sharing their data with various health-care entities furthermore enhancing information privacy.

Convolutional Neural Networks (CNNs) have demonstrated remarkable success in image recognition tasks, but their deployment on resource-constrained devices remains challenging due to their computational complexity and memory requirements. This abstract presents an overview of hardware accelerator implementations for CNN-based image recognition, focusing on techniques to optimize performance, energy efficiency, and resource utilization. Hardware accelerators such as Field-Programmable Gate Arrays (FPGAs) offer parallel processing capabilities that can exploit the inherent parallelism in CNN computations. Design considerations include optimizing memory access patterns, and minimizing communication overhead between processing elements. Techniques such as pipelining, unrolling, quantization, and network compression are employed to reduce the computational and memory footprint of CNN models without significantly compromising accuracy. Hardware-software co-design methodologies enable seamless integration of CNN inference engines with host systems, facilitating real-time image recognition applications. The computational time of the proposed CNN is lower compared to that of the recent research works. Additionally, the proposed hardware design exhibits reduced memory, power consumption, and resource utilization as compared with recent literarture for MNIST digit recognition with 98.9% accuracy.

Public lighting is a ubiquitous utility in cities to ensure the safety of people. In addition to playing a significant role in amending the comfort and safety of cities, street lighting causes substantial financial burden on governments to maintain its operation. Smart Light Emitting Diode (LED) street light system has become a prominent alternative to conventional street lighting systems with the involvement of Internet of Things (IoT). In this manuscript, a supercapacitor based smart street management system with energy autonomous capability has been proposed. It works in real-time and as an energy-saving alternative to prevent unnecessary electricity consumption of the street light. The average current consumption and power consumption of the system are 619.14$\mu$A and 2.022 mW, respectively. Three charging schemes have been investigated to find the optimized topology to harvest energy. The proposed device harvests energy from ambient sunlight and artificial light using a solar cell of 64 mm x 37 mm x 0.22 mm with maximum output power of 66 mW. LoRaWAN has been incorporated for communication, with a communication range of 761 m in real-world testbed. The operation characteristics and performance evaluation has been done based on implementing the system in field to ensure seamless operation.

Recently, harvesting natural energy is gaining more attention than other conventional approaches for sustainable IoT. System on chip power requirement for the internet of things (IoT) and generating higher voltages on chip is a massive challenge for on-chip peripherals and systems. In this article, an on-chip reliable energy-harvesting system (EHS) is designed for IoT with an inductor-free methodology. The control section monitors the computational load and the recharging of the battery/super-capacitor. An efficient maximum power point tracking algorithm is also used to avoid quiescent power consumption. The reliability of the proposed EHS is improved by using an aging tolerant ring oscillator. The effect of Trojan on the performance of energy-harvesting system is analyzed, and proper detection and mitigation mechanism is proposed. Finally, the proposed ripple mitigation techniques further improves the performance of the aging sensor. The proposed EHS is designed and simulated in CMOS 90-nm technology. The output voltage is in the range of 3–3.55 V with an input 1–1.5 V with a power throughput of 0–22 μW. The EHS consumes power under the ultra-low-power requirements of IoT smart nodes.

Security and energy-consumptiont are two conflicting challenges in the design and operation of the smart cities that use Internet-of-Things (IoT). Providing power to IoT things (i.e., sensors and their communications) is a challenge as battery have a limited lifetime, and their maintenance and disposal are costly and hazardous. System on chip (SoC) power requirements for IoT ultra-low-power realm is different and is a challenge for the design engineers to provide uninterrupted power. In this paper, a paradigm shift research that addresses a secure self-sustainable solar-energy harvesting system (EHS) with a security mechanism is proposed. This design incorporates Physically Unclonable Functions (PUFs) for the security of EHS along with an aging sensor for recycled IC detection. The control unit monitors the computational load, recharging of the battery, and security mechanism. Capacitor value modulation (CVM) is used for impedance matching between solar cell and converter during maximum power point tracking (MPPT) to avoid quiescent power consumption. The existing resources of EHS used for designing the PUFs and aging sensor. The secure EHS is designed and fabricated in CMOS 90nm technology. The resulting output is in the range of 3-3.55 V with an input 1-1.5 V. The proposed EHS is consuming 22 μW of power, that satisfies the ultra-low-power requirements of IoT smart nodes.

Listless set partitioning embedded block (LSK) and set partitioning embedded block (SPECK) are known for their low complexity and simple implementation. However, the drawback is that these block‐based algorithms encode each insignificant subband by a zero. This generates many zeros at earlier passes because the number of significant coefficients at higher bitplanes is likely to be very few in a transformed image. An improved LSK (ILSK) algorithm that codes a single zero to several insignificant subbands is proposed. This reduces the length of the output bit string, encoding/decoding time and dynamic memory requirement at early passes. Furthermore, ILSK algorithm is coupled with discrete Tchebichef transform (DTT). This gives rise to a novel coder named as hierarchical listless DTT (HLDTT). The proposed HLDTT has desirable attributes like full embeddedness for progressive transmission, precise rate control for constant bit rate traffic and low complexity for low power applications. The performance of HLDTT is assessed using peak‐signal‐to‐noise‐ratio (PSNR) and structural‐similarity‐index‐metric (SSIM). Extensive simulation conducted on various standard test images shows that HLDTT exhibits significant improvement in PSNR values from lower to medium bit rates. At the same time, HLDTT shows improvement in SSIM values on all bit rates.

A Fuzzy Logic Controller (FLC) is designed with heuristic knowledge of the plant. There are several application based Fuzzy Logic Controllers in literature. However, application specific controllers lack reusability and are expensive, if not produced in bulk. This paper presents a general purpose and easily configurable fuzzy logic based controller which can work with 4 inputs and generates a control action based on the knowledge base. Expert operator knowledge can also be directly programmed into the knowledge base (also known as rule base) of the designed controller without ceasing the control operation. The ease of file handling and user interactivity of DSP processors is heavily exploited and TMS320C6713 DSP was chosen as the hardware platform. Further this paper also analyses the system performance with reference to the Fuzzy Logic Toolbox of Matlab.