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Mike Ehrlich

dblp:116/7049 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 46% Interconnection networks and networks-on-chip · 30% Memory systems · 23%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache coherence
0.011998
StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues · SC 1998
Processor architecture and microarchitecture
multicore design
0.011998
StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues · SC 1998
Interconnection networks and networks-on-chip
network interface
0.011998
StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues · SC 1998
Processor architecture and microarchitecture › multiprocessor architecture
scalable shared-memory multiprocessor
0.011998
StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues · SC 1998
Interconnection networks and networks-on-chip › network interface
programmable network interface
0.011998
StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues · SC 1998

Methods — techniques the papers use, named apart from their topics

message passing · 0.0firmware · 0.0
YearPublicationVenuePosition
1998 StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues
abstract
This paper describes StarT-Voyager, a machine designed as an experimental platform for research in cluster system communication. The heart of StarT-Voyager is a network interface unit (NIU) that connects the memory bus of a PowerPC-based SMP to the MIT Arctic network. The NIU is highly flexible, with its set of functions easily modified by firmware or by programmable hardware, making it possible to compare different communication interfaces and implementation strategies on a common platform. Its flexibility comes from a fast embedded processor and large, fast FPGAs that surround a high-speed protected communication core. Its efficiency comes from a set of primitive operations that are implemented in hardware and are designed to reduce the firmware overhead. Our initial configuration of StarT-Voyager implements four forms of message passing along with S-COMA and NUMA shared memory support. With experimentation on the machine, it can be reconfigured to introduce new mechanisms improving usability and performance.
Boon Seong Ang, Derek Chiou, Daniel L. Rosenband, Mike Ehrlich, Larry Rudolph, Arvind 0001
SC4