Embedded systems are prone to leak information via side-channels associated with their physical internal activity, such as power consumption, timing, and faults. Leaked information can be analyzed to extract sensitive data and devices should be assessed for such vulnerabilities. Side-channel power-supply leakage from embedded devices can also provide information regarding instruction-level activity for control code executed on these devices. Methods proposed to disassemble instruction-level activity via side-channel leakage have not addressed issues related to pipelined multi-clock-cycle architectures, nor have proven robustness or reliability. The problem of detecting malicious code modifications while not obstructing the sequence of instructions being executed needs to be addressed. In this article, instruction sequences being executed on a general-purpose pipelined computing platform are identified and instructions that make up these sequences are classified based on hardware utilization. Individual instruction classification results using a fine-grained classifier is also presented. A dynamic programming algorithm was applied to detect the boundaries of instructions in a sequence with a 100 percent accuracy. A unique aspect of this technique is the use of multiple power supply pin measurements to increase precision and accuracy. To demonstrate the robustness of this technique, power leakage data from ten target FPGAs programmed with a prototype of the pipelined architecture was analyzed and classification accuracies averaging 99 percent were achieved with instructions labeled based on hardware utilization. Individual instruction classification accuracies above 90 percent were achieved using a fine-grained classifier. Classification accuracies were also verified when a target FPGA was subjected to different controlled temperatures. The classification accuracies on discrete (ASIC) pipelined-architecture microcontrollers was 97 percent.

Real-time electroencephalogram (EEG)-based state detection and prediction has many applications in Human-Computer Interactions, for example, adaptive training. Network analysis of brain activity derived from EEG data has been correlated to various cognitive states in the neuroscience literature making these network features an attractive measure to use for state detection. However, deriving these network measures in real-time is non-trivial and relatively unexplored in the literature. In this paper, we examine hardware designs and algorithmic performance of an existing non-linear measure of network activity, structural synchrony, as compared to a correlation-based linear measure of network activity, towards real-time human state classification. Our results indicate that the non-linear structural synchrony metric achieves a higher classification accuracy with similar computation speed. We demonstrate that the structure synchrony method can be accelerated in hardware using less resources while achieving similar latency and throughput. Collectively, our results suggest that a real-time implementation of non-linear, network connectivity measures on EEG data is viable and may facilitate on-line human state estimation.

Accessibility problems such as obstacles on sidewalks can make navigation dangerous for the visually impaired. Detecting these accessibility problems using embedded cameras is a plausible remedy. However, current computer vision algorithms for object detection rely on exhaustive search with high-dimensional features that present a heavy computational burden and incur a long latency, making them non-ideal for real-time object detection on embedded platforms. To address this problem, inspired by prior-based searching schemes from human vision, we accelerate the machine vision process by using scene-specific features to select candidate regions in the view for further processing. Our system, {\hav} achieves speedup by trading off the workload from on-line detection to off-line prior data collection and extraction. We demonstrate a complete, scalable PreSight prototype to accelerate general computer vision object detection algorithms with focus on detecting of sidewalk accessibility problems. Our prototype system automates the process of creating a geo- tagged database of object-specific priors using crowdsourcing and utilizes this prior knowledge to speedup object detection on embedded platforms. Evaluating under two benchmark object detection algorithms, we demonstrate that the detection latency can be reduced by around 8 times with the aid of PreSight.

Side-channel analysis techniques have been demonstrated for secret information extraction, vulnerability assessment and intrusion analysis. However, these techniques have not been applied to identify instructions running on a general purpose pipelined computing platform. In this work we identify instruction execution sequences on these platforms using side-channel power measurements. The technique uses a Principal Component Analysis (PCA) based model to generate multiple power-supply templates and a novel post-processing dynamic programming algorithm for optimal template matching. One unique aspect of this technique is that we take measurements on multiple power supply pins on the device, to increase the precision and accuracy. We apply our dynamic programming algorithm, to detect the sequence of execution clock cycles, on templates for single instructions that provides accuracy in the range of 69.2% to 87.5% for ten thousand observations, from individual power supply pins. We further augment this technique to generate multiple dictionaries for various length instructions and use data from multiple power supply pins to increases the accuracy in the range of 87% to 100%. Further, classification rates for instruction templates based on operand addressing mode and specific hardware used, range from 87% to 100% using as few as 10 principal components. Using our methodology, we can determine malicious insertions in a pre-determined code sequence with a 100% accuracy, as demonstrated in the results.

Activity recognition has applications in a variety of human-in-the-loop settings such as smart home health monitoring, green building energy and occupancy management, intelligent transportation, and participatory sensing. While fine-grained activity recognition systems and approaches help enable a multitude of novel applications, discovering them with non-intrusive ambient sensor systems pose challenging design, as well as data processing, mining, and activity recognition issues. In this paper, we develop a low-cost heterogeneous Radar based Activity Monitoring (RAM) system for recognizing fine-grained activities. We exploit the feasibility of using an array of heterogeneous micro-doppler radars to recognize low-level activities. We prototype a short-range and a long-range radar system and evaluate the feasibility of using the system for fine-grained activity recognition. In our evaluation, using real data traces, we show that our system can detect fine-grained user activities with 92.84% accuracy.

Evaluating and debugging solar panel-driven systems is a cumbersome process. The system must be deployed in the wild, software and hardware bugs identified remotely, and the development cycle must be repeated to build a robust system. Emulation platforms for solar panels offer a plausible remedy, however, existing systems have narrow operating range and are not portable. To address these shortcomings, we design, implement, and evaluate the SunaPlayer, a solar panel emulation platform that supports a wide operating current range (430 micro-amps to 1.89 amps) and voltage range (0.02 V to 9.8 V), and can be powered using batteries. SunaPlayer uses a high gain analog device, a PNP darlington transistor, a multi-scale driving and measurement circuit, and a novel state machine based proportional-integral-differential controller to build an accurate non-linear model of the solar panel. We have implemented a fully functional SunaPlayer prototype, and demonstrate that it can emulate a wide range of solar panels with high accuracy, low latency, high sensitivity, and low power consumption. The design methodology for the SunaPlayer can be used to build systems that model hard to emulate non-linear devices.

Tongue gestures are a key modality for augmentative and alternative communication in patients suffering from speech impairments and full-body paralysis. Systems for recognizing tongue gestures, however, are highly intrusive. They either rely on magnetic sensors built into dentures or artificial teeth deployed inside a patient's mouth or require contact with the skin using electromyography (EMG) sensors. Deploying sensors inside a patient's mouth can be uncomfortable for long-term use and contact-based sensors like EMG electrodes can cause skin abrasion. To address this problem, we present a novel contact-less sensor, called Tongue-n-Cheek, that captures tongue gestures using an array of micro-radars. The array of micro-radars act as proximity sensors and capture muscle movements when the patient performs the tongue gesture. Tongue-n-Cheek converts these movements into gestures using a novel signal processing algorithm. We demonstrate the efficacy of Tongue-n-Cheek and show that our system can reliably infer gestures with 95% accuracy and low latency.

Home automation and environmental control is a key ingredient of smart homes. While systems for home automation and control exist, there are few systems that interact with individuals suffering from paralysis, paresis, weakness and limited range of motion that are common sequels resulting from severe injuries such as stroke, brain injury, spinal cord injury and many chronic (guillian barre syndrome) and degenerative (amyotrophic lateral sclerosis) conditions. To address this problem, we present the design, implementation, and evaluation of Inviz, a low-cost gesture recognition system for paralysis patients that uses flexible textile-based capacitive sensor arrays for movement detection. The design of Inviz presents two novel research contributions. First, the system uses flexible textile-based capacitive arrays as proximity sensors that are minimally obtrusive and can be built into clothing for gesture and movement detection in patients with limited body motion. The proximity sensing obviates the need for touch-based gesture recognition that can cause skin abrasion in paralysis patients, and the array of capacitive sensors help provide better spatial resolution and noise cancellation. Second, Inviz uses a low-power hierarchical signal processing algorithm that breaks down computation into multiple low and high power tiers. The tiered approach provides maximal vigilance at minimal energy consumption. We have designed and implemented a fully functional prototype of Inviz and we evaluate it in the context of an end-to-end home automation system and show that it achieves high accuracy while maintaining low latency and low energy consumption.

Variations in the power-distribution network are exacerbated because of scaled supply voltages and smaller noise margins in sub-nanometer designs, which adversely affect performance and yield. Power-Supply noise incurred by excessive simultaneous switching of multiple paths negatively impacts the timing of a circuit. Supply noise is a major issue especially during transition and delay test where test vectors cause increased switching as compared to functional operation resulting in increase in path delays. Test rejects due to excessive noise-induced failures during delay and transition testing negatively impacts yield. Hence there is a need to accurately characterize the resistive and inductive voltage drop caused by excessive switching. To our knowledge, inductive drop has been excluded to simplify noise analysis. In our previous work, we have presented a convolution-based dynamic method (herein referred to as PSANDE) to estimate both IR and Ldi/dt drop on small combinational and sequential circuits. In this paper we show that the effectiveness of the design partitioning technique makes the framework feasible for a larger design. Our dynamic approach involves selectively simulating only extracted switching logic which makes the run-time tractable as compared to prohibitive full-chip SPICE simulations. We also present data to show that PSANDE can accurately predict the power-supply noise due to clock tree switching. Data presented in this paper for power supply noise is based on a large ITC'99 sequential benchmark b17 circuit. with a maximum error of 8.2% in comparison to full-chip SPICE results.

The aftermath of a natural disaster is characterized by lack of a reliable medium for dissemination of information to survivors. The state-of-the-art emergency response systems rely on satellite radio-enabled devices, but survivors, unlike first responders, do not have access to such devices. To mitigate this problem, we present perpetuu, a solar-powered portable GIS microserver. The microserver node can be deployed in a disaster scene and can serve maps to survivors viewable on browsers of off-the-shelf mobile systems. The perpetuu nodes can form a wireless mesh to cover a large geographic region. A key innovation in the design of the perpetuu node is a tiered software and hardware architecture—the system combines a low-power micro-controller with a high-power micro-processor to provide a large spectrum of power states. perpetuu stays in its lowest power state most of the time, and it can in-vitro detect survivors using Wi-Fi sensing, and consequently wake up the higher-power tier to disseminate high-resolution maps on standard web browsers that provide directions to safe locations. The tiered design leverages hardware-assisted energy measurements and a wakeup controller to balance energy harvested from solar panels with energy consumed by the system. We evaluate perpetuu using measurements from our prototype and trace-based simulations, and show that it can function near-perpetually while serving maps to a large number of survivors.

Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. We present a scalable current-based dynamic method to estimate both IR and Ldi/dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay caused by variations in power-supply voltage. This increase in delay can cause significant overkill during transition and delay testing. It is critical to account for this increase in delay during the ATPG process. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. To overcome this issue, our technique uses simulations of individual extracted paths and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for the C6288 ISCAS'85 benchmark circuit are presented. Our technique can also be applied to sequential circuits and simulation results demonstrating this are also presented.

Power Supply Noise has a significant impact on path delay and therefore its estimation is critical in delay testing. In deep sub-micron technologies, voltages are scaled and the number of switching gates has increased which make chips susceptible to power supply noise. Running full-chip simulations on large designs to predict the noise is time consuming and expensive. Therefore, most existing techniques are based on statistical approaches. In this paper, we propose a current-based dynamic method to estimate power supply noise and use the framework to predict the increase in path delay caused by the variations in power supply voltage without carrying out a full-chip simulation. A convolution-based technique is used to compute the path delays where standalone paths are extracted and simulated. Experimental results reported for estimating noise using the ISCAS-85 benchmark circuit are within 10% of full-chip results. The delay predictions carried out on two other experimental designs using our technique closely match full-chip results with a maximum error of 2%.

This paper demonstrates a computational image sensor capable of implementing compressive sensing operations. Instead of sensing raw pixel data, this image sensor projects the image onto a separable 2-D basis set and measures the corresponding expansion coefficients. The inner products are computed in the analog domain using a computational focal plane and an analog vector-matrix multiplier (VMM). This is more than mere postprocessing, as the processing circuity is integrated as part of the sensing circuity itself. We implement compressive imaging on the sensor by using pseudorandom vectors called noiselets for the measurement basis. This choice allows us to reconstruct the image from only a small percentage of the transform coefficients. This effectively compresses the image without any digital computation and reduces the throughput of the analog-to-digital converter (ADC). The reduction in throughput has the potential to reduce power consumption and increase the frame rate. The general architecture and a detailed circuit implementation of the image sensor are discussed. We also present experimental results that demonstrate the advantages of using the sensor for compressive imaging rather than more traditional coded imaging strategies.

This paper discusses the application of a computational image sensor, capable of performing separable 2-D transforms on images in the analog domain, to compressive sensing. Instead of sensing and transmitting raw pixel data, this image sensor first projects the image onto a separable 2-D basis set. The inner products computed in these projections are computed in the analog domain using a computational focal-plane and a computational analog vector-matrix multiplier. Since this operation is performed in the analog domain, components such as the analog-to-digital converters can be taxed less when a only subset of correlations are performed. Compressed sensing theory prescribes the use of a pseudo-random, incomplete basis set, allowing for sampling at less than the Nyquist rate. This can reduce power consumption or increase frame rate.

This paper describes a floating-gate transistor based analog implementation of adaptive filters that adapt based on the least-mean-square (LMS) learning algorithm. Floating-gate transistors are used for both weight adaptation and non-volatile weight storage. A current-mode approach results in a compact, low-power synapse. Experimental results from a prototype chip with a matrix of 16times4 synapses along with supporting circuitry fabricated in a 0.35 mum CMOS process are provided to demonstrate adaptation.

This paper discusses a 256times256 computational imager capable of performing separable transforms. Unlike traditional imagers, this imager performs computation on-chip and in- pixel. The primary computation performed is a separable matrix transformation. Several developments were made since a previous matrix transform imager to expand functionality and resolution. New circuit design emphasized dynamic range, accuracy, and speed. This architecture includes a novel overlapping block scheme allowing 8times8 general separable 2-D convolutions as well as 16times16 block transforms.

This paper describes a transimpedance amplifier using logarithmic compression of the input current for wide dynamic range current sensing applications. Measurements demonstrate operation over currents ranging from 200fA to 2μA with an average error of 0.8%. It is analytically shown that the power dissipation of the non-adaptive structure varies linearly with dynamic range. This amplifier alleviates this strong dependance on dynamic range and achieves low-power operation by adapting the bias current of the amplifier depending on input current thus burning an average power of 3.45μW per decade of current. Either SNR or bandwidth can be made to trade-off with the input current depending on application. If the bandwidth is limited to 5kHz, it achieves an average SNR of 65dB.

We propose an image processing system using an analog transform imager chip. The transform imager is a CMOS imager which is capable of block transforms using floating-gates. Because the transform imager is highly programmable, it can perform various block transforms such as the Walsh-Hadamard transform, discrete sine transform (DST), and discrete cosine transform (DCT). We investigate the reduction of computations and power by a baseline JPEG compression system as an application. The 48/spl times/40 transform imager provides 144 MOPS/s using an area of 1.03 mm/sup 2/ in 0.5 /spl mu/m CMOS technology, and it has a much higher fill factor, 46%, compared with other focal plane imagers. The measured transformed images and the reconstructed images are presented to demonstrate the operations.